Industry Insights - All Comments

The DVCon papers men ...

Anonymous — Fri, 12 Mar 2010 12:54:38 GMT

The DVCon papers mentioned in this blog are available in the Cadence Resource Library at www.cadence.com/.../default.aspx.

Where can I find the ...

Anonymous — Fri, 12 Mar 2010 09:37:20 GMT

Where can I find the two paper? Thanks.

Good points, Camille ...

rgoering — Tue, 02 Mar 2010 13:09:14 GMT

Good points, Camille. As noted in the DVCon Wednesday panel (and reported in my March 1 blog), using external IP that's not designed for integration may cause even more effort than doing a design from scratch. Adaptability and configurability are important, so long as the needed features are there. What will not work well is a "least common denominator" approach.

"This phase will rel ...

Anonymous — Sun, 28 Feb 2010 14:12:35 GMT

"This phase will rely on expertise in mixed-signal design and package design, both areas of strength for Cadence." -- Lip-Bu

I, as a principle EDA engineer, evaluated Cadence Mixed-Signal product two times (using real designs) in last five years at a CPU company and an analog company, both time the Cadence product shown clear advantage, and the product team has very strong members.

So, I agree with what Lip-Bu said. Wish Cadence continue lead the way.

I suspect that the l ...

Anonymous — Fri, 26 Feb 2010 08:11:56 GMT

I suspect that the lack of commercially available TLM IP is a factor in the reluctance to use outsourced IP but in many cases it is due to the erroneous perception that the effort to adapt the outsourced IP to internal needs is higher than internally sourcing it.

It seems like what is needed is a built-in IP 'adaptability by design' where attention is devoted to deconfigurability in addition to configurability to allow feature stripping and to simplify interfaces down to what is just needed. This also happens to make the task of RT and TLM matching a simpler proposition not to mention power savings and the like. I guess you may be able to get the 'transaction' right but what about the context/legacy and the boundary conditions that may not be easy to abstract?

Glad to see the new capabilities and standards being developed through OCP and the new startups and thanks for posting the helpful links.

we have a different ...

Anonymous — Thu, 25 Feb 2010 17:38:21 GMT

we have a different Verification team, challange is that Verification team don't find their job interesting & there is not growth path for them

Good points, Sean. E ...

Anonymous — Tue, 23 Feb 2010 09:46:07 GMT

Good points, Sean. EDAC does include "services" in its market statistics reports, but it's not a large number. I'm not sure what they're including. If we include Indian and Chinese IC design services as part of EDA revenues, that certainly changes the picture!

You need to update y ...

skmurphy — Sat, 20 Feb 2010 15:30:32 GMT

You need to update your blog picture, I didn't recognize you without your whiskers. This is a great summary, but my question is what did we learn. First, the things that have been true for a while (using your item numbering)

2. EDA must enable customer profitability

3. EDA tied to semiconductor R&D spend

4. Excess capacity only clear in hindsight

5. Moore's Law is running out of steam

7. Semiconductor industry is not consolidating but there is ongoing M&A

8. End markets are the ultimate driver

Two things that were now clearer

1. Growth looks to be flat for years

6. No quick recovery from immediate economic problems

Things that were mentioned last year that were not mentioned this year:

1. Promise of Green Technology

2. Promise of new Automotive Applications

3. Don't let a crisis go to waste

It was also interesting how Rhines characterized Mentor's acquisition process: "we believe that if you add the #3 tool base to the #4 you end up with 7th place; our acquisition strategy is to build on our strengths."

One question I was going to ask--it's a shame that Vleeschhouwer ran out the clock--was why the Indian service market is not included in EDA, it appears to be huge (at least based on an analysis by Olivier Coudert see www.ocoudert.com/.../why-service-companies-will-eat-up-eda in particular this paragraph:

More numbers? Let us only look at the VLSI service companies in India, i.e., in no specific order: HCL Technologies, KPIT Cummins Infosystems Ltd, MindTree Ltd, Sasken Communication Technologies, Tata Consultancy Services, Wipro Technologies. According to the India Semiconductor Association, VLSI design service revenues in India could hit $1.13 billion in 2009, while hardware and board design could reach $560 million and embedded design and services about $7.29 billion. Yes, that’s nearly $9 billion overall, nearly twice the EDA market, and China is not even in the picture yet. Despite the dramatic downturn in 2009, some of these services companies did quite well, and most expect an uptick with a recovery in the semi industry next year.

This is not an argument about outsourcing but a structural shift in the industry (and I think accounts for the EDAC's focus on anti-piracy as their #1 initiative).

Hi Richard, Anoth ...

Anonymous — Tue, 16 Feb 2010 20:33:04 GMT

Hi Richard,

Another one that is implicit in your post - With social media all of us sitting at different time zones & geographical boundaries are able to read a crisp summary of a relevant event which otherwise would have been missed out.

Thanks!

Dear Richard, I a ...

Anonymous — Sun, 14 Feb 2010 23:44:22 GMT

Dear Richard,

I am very happy that you raise the issue of student education and access to tools

and methodologies and reference to the Cadence Academic Network (CAN) as an initiative

to overcome the well-known insufficiencies in this area.

I am teaching a VLSI curriculum at TU Braunschweig, that was setup in close

collaboration with the nearby Intel labs with the specific goal to improve student education

such that the warmup phase for new hires in a company like Intel can be significantly reduced.

The CAN has been a formidable instrument in this challenging endeavour, not only by providing tools

and kits that - for the first time- offer the latest technologies for student education, but also

by providing a support network where you can share knowledge, experiences and methodologies with

others. Without this ecosystem, demanding technologies like e.g. power gating or MPSoC design would be out-of

reach for education. Having the students work with SoA industry tools and environments

reduces the training phase in the companies dramatically. Indeed we have had good experience

with students doing their master thesis at Intel that were able to work on top-notch

projects in just half a year of time.

I also fully appreciate your comment that we have to do more in the direction of letting the students work in

practical labs in small design teams that work _together_ to solve a larger project, not just individually.

Forcing them to interface with their peers helps raise their sensitivity for team work project management. Our experience

shows that they run into the typical hassles, e.g. communication & coordination problems that limit

the effectiveness of the teams in achieving their overall goals together. For the students this is typically an eye-opening

experience.

Having attended the “Industry Ready” Panel Discussion at the last CDNLife! India I was surprised by

the openness awareness of the Indian educational industrial establishment to these very same issues.

This clearly demonstrates to me that these challenges are global and that by connecting in networks like CAN we

can achieve a lot more and educate better engineers in the future.

Mladen

TU Braunschweig, responsible for Advanced VLSI Design curriculum

We may have a semant ...

Anonymous — Sat, 13 Feb 2010 05:39:34 GMT

We may have a semantic issue here with verification ("are we building it right") vs. validation ("did we build the right product"), but it seems to me that ASIC functional verification has many features generally lacking in SW verification. I'm not aware that executable metric-driven verification plans, functional coverage, and constrained-random test generation are typically used in the SW world. You are right, however, that many problems occur when hardware meets software. This is where advanced functional verification methodologies from the HW world can be very useful.

"The central problem ...

theASICguy — Sat, 13 Feb 2010 04:24:46 GMT

"The central problem is that software verification has no formalized methodology."

Richard, I don't think you meant that the way it sounds. Software validation has been formalized many times, by SEI thru CMMI, and in many other ways. It is a much more mature practice than ASIC validation.

I think the issue is when hardware meets software, like in these embedded systems, you have people outside their area of expertise. ASIC designers don't have the rigor or methods for software validation to apply to the drivers and such that they are validating. And software engineers don't understand everything about the hardware. Combine that with the task of integrating legacy control systems, like you describe, and an issue is bound to occur.

As for the car, I go back to something I was told years ago when I was working on a system that decided when to fire an airbag. "The car is just a lawsuit on wheels!"

Thanks for URL! Pres ...

Anonymous — Fri, 12 Feb 2010 08:48:47 GMT

Thanks for URL! Presentation includes Dilbert cartoons I forgot to mention.

Hi Richard, Very ...

Anonymous — Fri, 12 Feb 2010 08:26:03 GMT

Hi Richard,

Very thoughtful summary and it also brings to light the importance of asking a few simple questions before embracing social media for every communication effort. It is common for most communications agencies to present social media strategies while ignoring the contextual landscape in which the company and its customers exist. This summary is another step towards helping people deploy social media tools with the right approach, thought and expectations.

If you're interested ...

Anonymous — Fri, 12 Feb 2010 06:01:06 GMT

If you're interested, we have the slides from this event available here: