Industry Insights

Digital and Analog Verification – Round Peg in a Square Hole?

rgoering — Thu, 09 Feb 2012 15:00:00 GMT

Recently I wrote about a panel discussion that looked at ways of bridging the gap between analog and digital design. This blog post resulted in a lengthy discussion in a LinkedIn group that brought up the topic of verification. One commentator noted that analog and digital designers have very different interpretations of "verification," and concluded that "people have been trying for years to squeeze the round analog peg into the square digital hole."

This comment was a response to a panel discussion in which panelists were asked the following question: "In the digital world we talk about how 70% of the effort is spent in verification. How much time is spent in analog verification?"

Panelist Navraj Nandra (Synopsys) replied that the 70% estimate "is not far off but the color of verification is different." He explained that customers in the analog world are looking for things like IV numbers, and they expect silicon characterization.

Panelist Mladen Nizic (Cadence) noted that we need to distinguish functional verification from signoff verification. "If we talk about digital, it's usually just functional verification," he said. "We need to invest more in analog/mixed-signal functional verification. I see more and more adoption of digital techniques like coverage driven verification and random stimulus. This combination is really needed." For signoff verification, he said, a hierarchical approach can alleviate the need for heavy SPICE simulation runs.

Analog "Verification" is Part of Design

The LinkedIn commentator noted that there may be a more fundamental difference. While digital engineers view "verification" as a separate step, analog designers simply see it as part of the design process. The analog engineer develops an architecture, runs simulation to see if the architecture meets the specs, modifies the architecture if not, and runs the simulation again. Thus, verification is an iterative process, not something handed off to someone else.

If verification is part of the design process in a pure analog world, this could explain why we don't see separate verification teams for analog, as we do for digital. But wait a minute. The world is no longer pure analog or pure digital -- it is increasingly mixed-signal. Even "analog" IP blocks are likely to have some digital control logic, and nearly all "digital" systems-on-chip (SoCs) contain some "analog" (and mixed-signal) IP blocks.

It is at this intersection of analog and digital that a new verification paradigm is emerging -- at least, new for the analog folks. Techniques such as verification planning, random test generation, coverage, metric-driven verification, and assertions are in use today in mixed-signal settings, and they are working. Proof of this came in a Design Automation Conference 2011 panel that I moderated (photo below) at the Cadence booth in which engineers from Qualcomm, NXP Semiconductors, and LSI described how their companies are bringing digital verification techniques into the analog/mixed-signal world.

DAC 2011 mixed-signal panel (photo by Joe Hupcey III)

Among other topics, the engineers discussed real number (wreal) modeling, which allows ranges of analog values to be represented in digital simulation environments; the need for separate analog verification teams; the use of verification planning, analog coverage, and analog assertions; mixed-signal design with the Universal Verification Methodology (UVM); and the need for analog/mixed-signal language extensions to SystemC, SystemVerilog and UVM. You can read my report of the discussion here.

SPICE Forever?

Of course, SPICE simulation is still needed at the analog block level, and probably will be needed for many years in the future. Multi-core implementations of SPICE, like the Virtuoso Accelerated Parallel Simulator (APS), can be of great help in this regard. What is needed is a range of analog/mixed-signal modeling and simulation techniques, from SPICE to Verilog-AMS to real number modeling, so engineers can make the proper tradeoffs between speed and accuracy (below).

When it comes to mixed-signal SoCs, a separation between "analog" and "digital" is no longer relevant, and no IP block should be treated as a black box to be thrown over the wall to the other side. The interaction between analog and digital circuitry is one of the greatest sources of errors, and when you add low-power design techniques to the mix, it's even more hazardous. Thus, a thorough mixed-signal verification is essential, and it must be completed in a reasonable period of time.

How can this be done? What is needed is an integrated mixed-signal design and verification environment that combines the best of both analog and digital worlds, preferably using a common database such as OpenAccess. And digital techniques such as executable verification planning, assertions, and metric-driven verification must come along with this environment, along with wreal modeling at digital simulation speeds. This is how we get away from the "round peg into the square hole" problem. A point tool approach won't do it.

But even as analog and digital worlds become increasingly intertwined, we need to remember that words like "verification" can carry very different meanings in our respective worlds. In addition to adopting the right tools and methodologies, we need to learn to speak a common language, or at least begin to understand each other's dialects.

Richard Goering

Note: The recently published book Advanced Verification Topics has a detailed chapter on using metric-driven verification and UVM-MS (UVM with mixed-signal extensions) for analog/mixed signal design. You can read my review of the book here.

Customer, Partner DFM Concerns Spur New Methodologies

rgoering — Tue, 07 Feb 2012 14:00:00 GMT

Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies and methodologies that will be revealed next week (Feb. 12-16, 2012) in Cadence/customer co-authored papers at the SPIE Advanced Lithography conference in San Jose, California.

Philippe Hurat, product engineering director at Cadence, is the co-author of several "design side" DFM papers that will be given at SPIE. All describe engagements that Cadence has had with customers or partners. I talked to Hurat recently to learn more about these engagements and also about advanced-node DFM concerns in general. You can see a list of all Cadence co-authored SPIE 2012 papers (four of which concern computational lithography) in my previous blog post.

Customer Concerns

I asked Hurat what customers and partners are most concerned about at 28nm and below. "It depends on who they are," he replied. "Foundries are generally worried about printability, because a DRC-clean design that doesn't print still produces a bad yield. So most of the time, our work with foundries starts with printability or hotspot detection."

IC design houses, in contrast, are struggling with the integration of lithography or CMP checks into the design flow. A top priority, Hurat said, "is to make them more designer friendly. For the designer, having to run a DFM tool is a burden. So the easier you make it, the faster it is and the more automated, the less disruptive it is."

Moreover, he noted, variability has a big impact. At 28nm and even more so at 20nm, stress can cause significant timing variability, and layout dependent effects (LDE) become critical - that is, transistor performance will vary according to what is placed near it in the layout. Custom designers, library developers and chip designers must analyze and mitigate the impact on timing.

The Design House View

One of the SPIE DFM papers, In-design hierarchical DFM closure for DFM-clean IP, describes work that Cadence did with Freescale on manufacturability checks for litho and CMP at 28nm. "When you develop an IP block you want to make sure it is litho and CMP clean," Hurat said. "So we worked with Freescale to develop IP integration that fits their needs, and the paper will explain those requirements and how we achieved them for both litho and CMP." He explained that "CMP clean" is a tough requirement because CMP, unlike litho, has an effect over a large area that might go beyond the IP itself.

A second Cadence-Freescale paper is titled Analysis of layout-dependent context effects on timing and leakage at 28nm. This paper notes that at 28nm, the context - the layout surrounding a cell - impacts the timing and leakage of a cell due to stress and other LDE. It is one of several SPIE papers that describe the use of the Cadence Litho Electrical Analyzer (LEA) to analyze variability.

Another paper that discusses LEA and LDE is co-authored with Cambridge Silicon Radio and is titled Analysis, quantification, and mitigation of electrical variability due to layout-dependent effects in SoC designs. While the Freescale LDE paper is more focused on leakage and silicon results, the Cambridge Silicon Radio paper is primarily concerned with delay and mitigation strategies.

The Foundry View

Cadence and Samsung are presenting a paper titled In-design process hotspot repair by pattern matching. This paper demonstrates a pattern-based approach for hotspot repair developed by Samsung that is much faster than traditional lithography simulation. Hurat noted that Cadence provided the entire flow, from pattern creation to pattern detection and hotspot fixing in place and route. (Note: The Cadence-Samsung partnership in DFM is further described in a Feb. 6 press release).

Finally, Cadence and GLOBALFOUNDRIES co-authored a paper titled Electrical design for manufacturability and layout-dependent variability hotspot detection flows at 28nm and 20nm. This paper is aimed at custom/analog design with the Cadence Virtuoso platform, and it shows that lithography as well as stress is a major source of LDE variability.

For more information about the Cadence co-authored papers, click here. A complete SPIE program is located here.

On the Manufacturing Side

In addition to these DFM papers, the above links will show you four papers that describe work that Cadence has done with partners on the "manufacturing" side of DFM (or, "computational lithography"). As Hurat noted, this is originally what SPIE was all about - design-side DFM was only added recently. Topics of the computational lithography papers include model calibration, source-mask optimization, self-aligned double patterning, and lithography target optimization.

If you're interested in DFM from any angle -- design or manufacturing, foundry or design house, custom/analog or digital -- SPIE 2012 is the place to be next week.

Richard Goering

Webinar Report: New Methodology Revs Up Code Coverage Analysis

rgoering — Mon, 06 Feb 2012 14:00:00 GMT

Most IC verification teams use code coverage as signoff criteria, but they often have limited information about unreachable code. A new "case-splitting" methodology, described in a recently archived webinar, shows how a technique based on formal analysis provides new insight into coverage holes -- while requiring no understanding of formal analysis.

The webinar is titled "Simplifying Code Coverage Analysis: Automatically Separating the Wheat from the Chaff." It was presented by Joe Hupcey, Cadence product marketing director, and Jose Barandiaran, senior member of consulting staff.

Barandiaran began the webinar by talking about the "dead code challenge." There are two causes of unreachability, he noted. One is that the code is "illegal" in the sense that it was never intended to execute - perhaps the code came with externally acquired IP and the system doesn't use that particular functionality. That's generally okay. The other cause is that the code is supposed to be functional, but it's unreachable. That is not okay.

Are Coverage Holes Reachable?

However, it is often difficult to determine whether coverage holes are unreachable. That's where the case-splitting technique comes in. It leverages formal analysis (using Incisive Formal Verifier or Incisive Enterprise Verifier) "under the hood" to determine if holes are reachable. It's an automated flow in which properties are automatically generated, and no knowledge of formal analysis is required.

The diagram below shows how it works. You pass a simulation coverage database to the formal engine, along with a reused, or newly created, simulation snapshot. You select either module or instance-level analysis, and identify the code coverage targets for the formal engine to analyze. The formal tool generates the properties and runs them. The tool then reports unreachable holes, and back-annotates them into the coverage database so you can go into a reporting tool later and analyze each one, determining whether they represent code that's supposed to be functional and thus needs to be fixed.

Barandiaran noted that there are some performance tradeoffs to consider. Out of the box, this flow will run without any constraints, and it will run uninitialized. That's the fastest approach but it may also miss some unreachable coverage holes. You can dial up the constraints and/or initialization and run more slowly, but hit more unreachable holes.

In one customer example shared during the webinar, an uninitialized run on a design with 40K state bits uncovered 773 coverage holes in 2.8 hours, with 7.6% of the holes unreachable. An initialized run found more unreachable holes (10% of 773), and ran for 35 hours. However, this run time was cut to 5 hours because the flow was distributed over a CPU network.

This example, and others presented during the webinar, shows that this case-splitting methodology is in use today by customers. "This has been exercised in the field. It's not just some lab experiment. It really works quickly and cleanly, and you get the data in a very straightforward manner," Hupcey said.

The webinar also included a demo, in which it took only a few minutes to find 33 coverage holes, of which 9 were unreachable. "If you have the tools already, this is really a no-brainer," Barandiaran said.

The webinar is available to Cadence Community members here (quick and easy free registration if you're not a member). If you already have the Incisive Enterprise Verifier, see chapter 5 of the user guide for an explanation of the case-splitting technique.

For those who want to know more, a paper from CDNLive! India 2011 details Freescale's experience with the case-splitting technique. It is available to Cadence Community members here. Look for session 1.6 under track 1, Silicon Realization: Functional Verification.

Richard Goering

Panelists: Bridging the Gap Between Analog and Digital Design

rgoering — Thu, 02 Feb 2012 00:00:00 GMT

Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow, opening the door to new methodologies and better collaboration, according to panelists at the DesignCon conference Jan. 31.

The panel was provocatively titled "Is it Time for an Analog Comeback?" and was moderated by Brian Bailey (right), contributing editor at EDN. Panelists were as follows:

Harold Joseph, director of PSoC analog, Cypress Semiconductor
Jeff Miller, director of product management, Tanner EDA
Navraj Nandra, director of marketing for analog/mixed-signal IP, Synopsys
Mladen Nizic, engineering director for mixed signal, Cadence
Warren Savage, CEO, IPextreme

Bailey opened the discussion by describing the status quo. "In the past analog and digital were really kept separate," he said. "It really was an oil and water situation." There are many differences between the two worlds - digital design is top-down, analog is bottom-up; digital is automated, analog is primarily manual. "There are so many areas of conflict between [analog and digital] that they are almost antagonistic to each other, especially when put in the proximity of a chip," Bailey said.

He noted, however, that 70% of IC designs today are mixed-signal, and that figure is increasing. "We have to start thinking about how we play together as a team rather than as pieces that are forced to come together," Bailey said. And that challenge set the stage for the following discussion.

Why Hasn't Analog Kept Up?

In his opening remarks, Miller (Tanner EDA) asked, "why hasn't analog design kept pace? The main thing is that the process for analog design is totally different from digital, and there has been no significant automation such as the place and route technology that has revolutionized digital." Miller said, however, that he sees a "bright future" for mixed-signal design in two respects - integration into large SoCs, and the addition of digital content to traditional "analog only" chips.

Nandra (Synopsys) spoke of some of the challenges that analog IP developers are encountering, such as the need to integrate analog components onto chips at advanced process nodes. For example, restricted design rules at these nodes limit the way full-custom devices can be placed and routed. He also noted that some system specs don't change with scaling - USB still requires a 5V signal to charge the battery, a challenge for advanced-node SoCs.

Nizic (Cadence) observed that some design teams are seeking to "economically" design mixed-signal SoCs at advanced process nodes, while others are working to bring more digital functionality, such as microcontrollers, into "mainstream" analog ICs at mature process nodes. Previously, he noted, analog circuitry might have taken 15-20% of the area of an SoC; today, at advanced nodes, it's likely to be 50%. And most of those SoCs use low-power design techniques, making things even more challenging.

"Many different skills are required to realize a design in silicon, and it is important that people with these skills work as a team," Nizic said. "Does it mean everybody has to become a mixed-signal designer? Certainly not." He noted that "we are striving to bring more unified technologies and highly integrated tools to enable that cooperation."

While other panelists talked about increasing mixed-signal integration, Savage (IPextreme) observed that many analog functions are still implemented off-chip, and he said he's seeing a trend towards "separation" of analog and digital. "Ten years ago we were talking about integrating everything into an SoC. That's true to an extent but I'm also seeing companies that are re-segregating." Savage said that 3D-ICs will offer the "best of both worlds" by integrating digital SoCs with optimized analog dies.

Following are answers to several questions posed to panelists.

Q: Do We Have Enough Analog Designers?

Miller: "There is great difficulty in training analog designers. It's not like digital where you learn the tools and you're sort of set. There's a lot of art in creating an analog cell."

Nizic: "We do have to nurture that [analog] skill. It does require more understanding of device physics to design good circuits. We need tools to make it easier. Reuse is very important as well."

Nandra: (Describing the design of PHY IP in 50 different process nodes) "It doesn't require genius engineers. What it requires is more like a factory to be able to stick to the same specs, but to design that [PHY] in different process nodes."

Q: Is There Any Hope for Analog Automation?

Nandra: "When building baseline transistor cells, we hide a lot of the process effects from engineers...In advanced nodes, we get a lot of EM problems because metal lines are thinner. Somehow we have to figure out how much current goes through these metal lines. That's a technique that can be automated."

Miller: "Selling automation to an analog design team is very difficult. You really need to give them control and try not to take too many pieces away."

Nizic: "Traditionally we assumed that analog is bottom up and digital is top down, but we are looking at mixed-signal systems now, so we really have to combine these approaches...We do have a lot of automation in our tools."

Savage: "Analog is an old school discipline...it is very hard for EDA companies to make tools that replicate the expert engineer, like we did 15 years ago with digital synthesis."

Q: In the Digital World We Talk about Verification Taking 70% of the Effort - Is This True in Analog?

Nandra: "It's not far off in that perspective, but the color of verification is different...our customers want to see the silicon characterization."

Nizic: "We need to distinguish functional verification from signoff verification. We need to invest more in analog/mixed-signal functional verification. I see more and more adoption of digital techniques like coverage driven verification and random stimulus. This combination is really needed."

Conclusion: Is it Time for an Analog Comeback?

Nandra: "Analog never disappeared. I disagree with Warren's comment about the ‘old school of analog.' I think there is a very exciting new school of analog that's a lot more interesting than some innovations in digital."

Joseph: "We're starting to see SoCs address some issues, but we've never seen analog go away."

Savage: "Analog never really went away. One big change today compared to when I was a younger engineer is that analog is sexy now."

Miller: "There have been historical shifts. I do think the pendulum will swing back a bit and we'll try to do things in analog if at all possible."

Nizic: "Analog never really went away. SoCs have more and more mixed signal content. This is a window of opportunity for better methodologies."

Bailey: "I conclude that analog is a place for renewed innovation and renewed differentiation, and it's sexy again."

Richard Goering

Whitepaper: Verification Performance is More Than Raw Simulation Speed

rgoering — Tue, 31 Jan 2012 14:00:00 GMT

RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster, please!" As a recently published Cadence whitepaper shows, verification turn-around time does require faster simulation engines, but it involves much more than that.

The whitepaper is titled "Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements." It shows what is necessary to improve verification productivity for advanced-node chips, and notes recent improvements in the Incisive Enterprise Simulator that are aimed at performance scaling. The paper advocates a project-specific, "systematic" approach in which users first analyze the design and verification requirements to identify possible improvements. With significant testbench or design changes, a detailed profile is necessary to identify performance bottlenecks.

The whitepaper notes briefly that one way to increase verification turn-around time is to move to a higher level of abstraction, such as transaction-level modeling (TLM). There are also mentions of formal verification, acceleration, and emulation as productivity boosters. But for the most part the whitepaper focuses on how to get better and faster results with RTL and gate-level simulation.

Speeding Up the Core Simulator

What can be done to speed up the core simulator? Quite a lot, actually. The whitepaper describes some improvements made to the Incisive Enterprise Simulator during 2011, including:

Assertion-based verification - A single finish for each cover property, optimizations focused on SystemVerilog assertions (SVA) sequence operators, and performance controls speed both subsystem and full SoC verification.
Gate-level simulation - Complex expressions in timing outputs have been optimized.
Coverage - Optimizations for mixed-language dumping, dynamic SystemVerilog objects, and toggle coverage contribute to runtime improvements; other optimizations minimize memory usage.
Power-aware design - A native low-power solution has marginal overhead during both elaboration and run time.

The whitepaper shows how to configure a simulator for speed by arriving at the best tradeoff between performance and debug access. By default, Incisive runs in a fast mode with minimal debugging capability. Some debug options should be applied selectively rather than locally, or should not be used for regression.

The whitepaper also notes how CPU, cache, memory, storage, network, and operating system affect performance. (Note: I wrote recently about how Cadence IT experts are helping customers with these kinds of issues). The whitepaper recommends that project teams profile the simulation environment regularly, and shows how this is done.

Advanced Node Verification Requirements

While tuning the simulation engine can provide single-digit performance multiples, the whitepaper notes, advanced-node teams really need to focus on turn-around time at each stage of verification. Quite often the elaboration phase consumes significant time. Incremental elaboration is an Incisive feature that can help.

Turnaround time affects each verification stage for advanced node SoCs

The whitepaper also shows how dynamic reseeding saves regression time. It notes how multi-core operation speeds regression runs. It concludes with a discussion of the productivity gains provided by formal verification and hardware-based acceleration.

In short, this whitepaper is a great read for anyone who wants a more productive verification environment. Turn-around time, adequate coverage, and quality of results are the real goals - and "wall clock" time on a simulator is a means to get there, but is by no means the entire picture.

For further perspectives, see Adam Sherer's recent blog post.

Richard Goering

Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

rgoering — Mon, 30 Jan 2012 14:00:00 GMT

DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in three increasingly critical areas for system-on-chip (SoC) design - low power, mixed signal, and the move to a higher abstraction level with SystemC.

Following are some suggested events in each of the three areas noted above. This is not a complete conference schedule - for that, see the DVCon web site. That is also where you'll find registration information. In addition to the paid conference passes you can get a free Exhibits Only pass that includes both of the scheduled panels and the keynote speech.

Transaction Level Modeling, SystemC, and HW/SW Co-Verification

North American SystemC Users Group 17^th meeting - Monday Feb. 27, 8:30 am - 12:00 pm. Speakers from Texas Instruments, Doulos, University of Paderborn, Cadence, University of Pennsylvania, Duolog. FREE registration at http://www.nascug.org/.

Town Hall Lunch with Accellera Systems Initiative - Monday 12:00 pm - 1:00 pm. Stan Krolikoski of Cadence, Accellera Systems Initiative secretary, will host this open meeting to answer the question, "What will success for the Accellera Systems Initiative look like?"

Last year's Accellera - OSCI "Town Hall" meeting at DVCon

Tutorial: An Introduction to IEEE 1666-2011, the New SystemC Standard - Monday 1:30 pm - 5:00 pm. John Aynsley of Doulos gives a detailed view of the revised standard.

Co-located Meeting: Hardware/Software Co-Design from a Software Perspective -- Monday 6:00 - 8:30 pm. Sponsored by EDAC Emerging Companies Committee.

Session 3: SystemC and Beyond - Tuesday 9:30 am - 11:00 am. Papers from University of Paderborn, PMC-Sierra, and Paneve LLC.

Session 7: Verification and Debugging Tips - Wednesday 8:00 am - 10:00 am. Includes Cadence paper on memory debugging of virtual platforms with TLM 2.0.

Panel: Build or Buy - Which is the Best Practice for Hardware-Assisted Verification? Wednesday 3:30 pm - 4:30 pm. Brian Bailey moderates this panel on emulation and FPGA-based prototyping. Panelists from Qualcomm, ARM, SpringSoft, Xilinx and Cadence discuss the tradeoffs between these solutions and the pros and cons of purchasing versus building in-house.

Low-Power Design and Verification

Session 1: Low Power Techniques - Tuesday 9:30 am-11:00 am. Charles Dawson of Cadence moderates the first conference session with presentations from Mentor Graphics, Cadence and Synopsys. Cadence paper focuses on low-power equivalence checking.

Cadence Sponsored Lunch - Earn Your Degree in the Low-Power Arts and Sciences. Tuesday 12:30 pm - 2:00 pm. Cadence and user experts will lead verification engineers and managers in a lively low-power discussion.

Mixed-Signal Verification

Poster Session 1 - Tuesday 10:30 am - See Cadence papers on "PSL/SVA assertions in SPICE" and "New challenges in verification of mixed-signal IP and SoC design."

Session 6: Mixed-Signal Verification - Tuesday 11:00 am - 12:30 pm. Papers from Maxim/Cadence, Infineon, Mentor Graphics. Maxim paper provides a case study of applying UVM-MS to a complex mixed-signal SoC design.

Session 8: Getting to Coverage Closure - Wednesday 8:00 am - 10:00 am. Includes Cadence paper on "Bringing continuous domain into SystemVerilog covergroups."

And Wait - There's More

More traditional verification topics (I'm including "formal" in this category) will also get thorough coverage at DVCon. Here is what you can expect.

Monday Feb. 27 features a full day of Universal Verification Methodology (UVM) tutorials, an introduction to the Unified Coverage Interoperability Standard (UCIS), and a tutorial on verification automation using IP-XACT.

Tuesday Feb. 28 includes sessions on UVM Techniques, Verification Benchmarking, and Formal Techniques. Exhibits run 3:30 - 6:30 pm. Speakers for a "Big Wigs" panel at 2:30 pm had not been publicized at the time of this writing (check back here).

Wednesday March 1 includes sessions on Verification and Debugging Tips, Coverage Closure, UVM in a Multi-Platform World, UVM Stimulus Generation, Verification Case Studies, and SystemVerilog Tips and Techniques. The keynote address will be given by Aart de Geus, Synopsys CEO. Exhibits run 4:30 - 7:00 pm.

Thursday March 2 concludes the conference with half-day tutorials on formal analysis "apps" (sponsored by Cadence), verification of multi-core SoCs, leveraging formal verification throughout the design cycle, and verification IP productivity.

See you at DVCon!

Richard Goering

SPIE Papers Showcase DFM and Lithography R&D

rgoering — Thu, 26 Jan 2012 14:00:00 GMT

Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing phase. The papers will be given Feb. 14-16 and are all co-authored with customers or partners.

According to Manoj Chacko, product marketing director at Cadence, "design side" DFM includes such topics as layout-dependent effects (LDE) and electrical variability for custom and digital designs, pattern matching based in-design DFM signoff, in-design litho hotspot repair, in-design chemical mechanical polishing (CMP) analysis, and hierarchical closure for IP blocks.

As reflected in the SPIE 2012 papers, Cadence R&D efforts in DFM have focused on quantifying the impact and minimizing the differences caused by LDE, building the yield detractor pattern infrastructure for leveraging pattern matching for litho signoff, estimating CMP effects for IP blocks, and allowing signoff-quality analysis during the design phase (see my earlier post on in-design DFM signoff here).

Computational lithography, which takes place after design rule checking (DRC), includes double patterning, source-mask optimization, and optical proximity correction (OPC) including OPC verification. Chacko said that Cadence is using "third generation" inverse lithography techniques to boost OPC, providing high-capacity full-chip dense OPC verification, and offering accurate model calibration. Cadence also does source and mask optimization concurrently.

The ten Cadence co-authored papers are listed below. Note that SPIE is organized into different "conferences" in such areas as extreme ultraviolet lithography (EUV), metrology, advanced lithography, DFM, and advanced etch technology. A complete SPIE program is located here. To read abstracts of these papers, click here.

SPIE Papers - Design Side DFM

Analysis, quantification, and mitigation of electrical variability due to layout-dependent effects in SOC designs
Paper 8327-14 of Conference 8327
Date: Wednesday, 15 February 2012
Authors from Cadence, University of Southampton, and Cambridge Silicon Radio

Electrical design for manufacturability and layout-dependent variability hotspot detection flows at 28 nm and 20 nm
Paper 8327-40 of Conference 8327
Date: Wednesday, 15 February 2012
Authors from Cadence and GLOBALFOUNDRIES Singapore

Analysis of layout-dependent context effects on timing and leakage in 28 nm
Paper 8327-17 of Conference 8327
Date: Wednesday, 15 February 2012
Authors from Cadence and Freescale

CMP effect due to perimeter: a perimeter drive dummy fill optimization approach
Paper 8327-37 of Conference 8327
Date: Wednesday, 15 February 2012
Authors from Cadence and Samsung

In-design hierarchical DFM closure for DFM-clean IP
Paper 8327-31 of Conference 8327
Date: Wednesday, 15 February 2012
Authors from Cadence and Freescale

In-design process hotspot repair by pattern matching
Paper 8327-27 of Conference 8327
Date: Thursday, 16 February 2012
Authors from Cadence and Samsung

SPIE Papers - Computational Lithography

Model calibration and full-mask process and proximity correction for extreme-ultraviolet lithography
Paper 8322-55 of Conference 8322
Date: Thursday, 16 February 2012
Authors from Cadence and Applied Materials

Self-aligned double patterning (SADP) compliant design flow
Paper 8327-5 of Conference 8327
Date: Wednesday, 15 February 2012
Authors from Cadence and GLOBALFOUNDRIES

Free form source and mask optimization for negative-tone resist development for 22nm node contact holes
Paper 8326-31 of Conference 8326
Date: Wednesday, 15 February 2012
Authors from Cadence, Applied Materials, and FUJIFILM Electronic Materials)

Lithography target optimization with source-mask optimization
Paper 8326-100 of Conference 8326
Date: Wednesday, 15 February 2012
Authors from Cadence and GLOBALFOUNDRIES

Cadence will be holding private briefings and demonstrating DFM and lithography solutions Feb. 14 and 15 for advanced-node ICs using custom/analog (Virtuoso) and digital (Encounter) environments. Further information is located here.

Richard Goering

Webinar Report: Power-Aware Mixed-Signal Verification

rgoering — Wed, 25 Jan 2012 14:00:00 GMT

Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware") verification must encompass both analog and digital - but how?

A recently archived Cadence webinar has some answers. Titled "Advanced Technology to Verify Complex Mixed-Signal Designs," the webinar was presented by Prabal Bhattacharya, simulation architect at Cadence. The webinar covered advanced mixed-signal verification topics including parasitic simulation, assertions, and low power. A recent blog post summarized the first part of this webinar; this post focuses on the last portion, which described power-aware mixed-signal verification using the Common Power Format (CPF).

Bhattacharya started this portion of the webinar by reviewing some basic concepts and showing how they apply to mixed-signal circuits. These concepts included power domains, state loss, isolation, power shutoff, and multiple supply voltage (MSV). In the latter case, he noted, supply voltage may vary from 1.2V to 1.8V or higher based on whether various conditions are true or false. This means the operating voltage of the block is dynamically changing during simulation.

"I think the primary challenge is that you have to do the conversion of the circuit's signal and low-power information," Bhattacharya said. "It is not enough to take an analog signal and bring it to the digital level, or a digital signal to the analog level. You have to think of the low power intent of that analog or digital block."

So how to do that? Earlier in the webinar, Bhattacharya introduced the concept of logic-to-electrical and electrical-to-logic "connect modules" that are automatically inserted by the simulator. In discussing low power, he introduced "power aware" connect modules. Shown below is a power-aware connect module (CM) that does a logic-to-electrical conversion using the power intent information in a CPF file. In this example a digital driver in a power domain (PD1) is driving an analog block in another power domain (PD2). The connect module takes power into account as it does the value conversion for the analog block.

Bhattacharya also talked about dynamic macro-model verification. A macro-model is typically a black box with no information about what's inside it. Thus, a chip-level verification engineer will focus on its boundary. However, he or she may need to verify that the analog value on an output port, as specified by CPF, matches the value that SPICE sees from the inside of the port. Bhattacharya showed how engineers can write a Property Specification Language (PSL) assertion to verify that the output voltage is within a desired range of tolerance.

"The main thing we want to emphasize is that the connect modules need to be power aware," Bhattacharya concluded. "You should be able to keep reusing your CPF specification even though some blocks are analog. You can do dynamic verification or assertion-based verification at the boundary to verify your low power intent."

You can access the archived webinar here. It's available free to members of the Cadence Community - quick and easy signup if you're not.

Richard Goering

Q&A: Frank Schirrmeister Updates Status of System-Level Design

rgoering — Mon, 23 Jan 2012 05:00:00 GMT

Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine site, a column in Electronic Design, and regular contributions to the Cadence System Design & Verification blog.

In this Q&A interview he discusses how he got into system-level design, the pace of adoption today, the promises and challenges of virtual prototypes, the progress of high-level synthesis, and the range of prototypes needed for hardware/software integration.

Q: Frank, what does your job at Cadence involve?

A: I'm responsible for product management of the System Development Suite, which includes virtual prototyping, RTL simulation, emulation, and rapid prototyping. I started in August [2011] but it's not the first time I've been at Cadence. Cadence recruited me and brought me to the U.S. in 1997 to run the Felix [system level design] initiative.

Q: How long have you been working with system-level design, and how did you get drawn into it?

A: I'm in my 15^th year. I was a chip designer originally. In 1993, I designed an HDTV encoding system for Deutsche Telekom [German telecommunications provider]. It had 6 or 7 chips and they were very complex for the time. I was involved in the architectural aspects, and I was fascinated with how these motion estimation chips fit into a systems context.

Prior to that time, I was an EE student at the Technical University in Berlin. I did some embedded software development for musical instruments to finance my time at the university. I studied what they called Technical Computer Science, and microelectronics was one of my focus majors. So, I started on the software side and then I did the hardware side as well. I even did full custom layout for one of the [HDTV] chips.

Cadence recruited me in 1997 because they were looking for people who had chip design and software development experience.

Q: How do you define system-level design or ESL [electronic system level]? Are these still useful terms?

A: I think they are useful terms to describe the portion of the design flow before you get to verified RTL. Because we have been talking about it for so long, ESL has a little bit of a negative connotation today, so I refer to it as system-level design. To make the term useful, the key question is what you define as a system. You need to define the boundary of what you mean by "system" carefully. The designer's system - like a system on chip [SoC] - becomes just a component of the phone, which is a component of the network.

Q: System-level design, or ESL, was certainly slow going for a number of years. Are you seeing more interest and adoption today?

A: I certainly do. When I started in this area in 1997, leading edge customers were looking at it as something they thought they would have to resolve, but you could really only get into the leading edge customers. This has changed. About five years ago people started to resonate with it more. Today when we go to a customer, he no longer has to be convinced he has a problem. The question becomes, how can Cadence help?

System-level design is still far away from mainstream, however. I would say it's still in early stages with lots of room for growth.

Q: Are virtual prototypes (or virtual platforms) coming into more widespread use? What obstacles are standing in the way to broader adoption?

A: Adoption is growing, and we have more and more people considering it, but I wouldn't call it mainstream yet. Most projects are still running without virtual platforms. One obstacle is that the people who have all the information to build the platform are hardware people, but the software developers are the users who get most of the value. It's kind of like doing something so your neighbor's life is easier.

Another obstacle is that existing methods for software development haven't totally failed yet. It's hard to develop on a board, and the boards are latest in the development cycle, but people try to get by with traditional techniques because the cost to build the virtual platform is still pretty high. It's expensive today because it's not a by-product of the traditional design flow.

Q: Both virtual prototypes and high-level synthesis use SystemC transaction-level modeling (TLM), but the models for high-level synthesis require much more detail. Can we bridge the gap and connect virtual prototypes to the implementation flow?

A: That's the next step that we're eager to get to. We want to enable a flow that takes the same architectural intent and leads into both software enablement and hardware implementation with high-level synthesis. Virtual platforms are expensive today because it's hard to build new models, and there is a lack of existing models for the re-used IP. If high-level synthesis could create, as a by-product, descriptions of new blocks that can be used for software development, that would be great. Then, if every IP provider would provide models, the problem would become mostly a TLM IP assembly issue.

Q: What are you seeing in terms of adoption for high-level synthesis?

A: What I find impressive about high-level synthesis is that it is silently being adopted by more and more customers, which means that vendors have to be involved in fewer of the projects directly. It's really in production. We have customers who are approaching or have 50 or more tapeouts with it. Datapath is the traditional sweet spot, but they're also using it for control. High-level synthesis is not only for datapath any more.

Q: What's the role of verification in facilitating the move from RTL to TLM?

A: Verification is a key driver in bringing about a jump to the next level of design entry. If you can verify at a higher level of abstraction, you can run more cycles and also different verification tasks - like application verification -- because execution is faster, albeit with less detail. It's kind of comparable to what happened with the move from gate-level to RTL simulation.

Today we're seeing a lot more people using TLM verification, and they're also bringing in software. There are two trends. First, a lot of testbenches themselves run at a high level of abstraction, and customers verify at the TLM level first and then add more detail. Secondly, people are using embedded software-driven verification, where their testbench is actually embedded software running on a processor they would have in the system. So they're running directed tests in software but the intent is to verify the hardware.

Q: Besides virtual prototypes, what kinds of prototypes are needed for hardware/software integration?

A: As I wrote in a recent EE Times article, you need prototyping throughout the flow at different stages. With virtual prototypes you get good speed for software debugging, but you don't get the accuracy you need for hardware verification. So you first bring in RTL simulation, which is in a sense a prototype, but it doesn't execute software very well. That's when you bring in emulation. Now higher-speed software development and execution become feasible, you have better debug on the software side, and you still have good debug insight into hardware.

But at some point that is still too slow as well, so you may want to bring in an FPGA-based prototype where you have even more speed. But what you have to take into account for FPGA-based prototypes is that every change you make on the hardware side takes longer. So you want to use it at a more stable phase of the RTL. At Cadence, we provide technology that allows you to reuse what you've done in the Palladium emulator to make the FPGA-based prototype bring-up easier.

Q: How does the Cadence System Development Suite address the challenges of hardware/software integration?

A: The idea behind the suite is that you can connect the different [prototyping] engines and enable an easy transition between the engines. For example, the Incisive RTL verification environment and the Virtual System Platform are based on the same technology, so bringing together RTL models and virtual prototypes is a very natural undertaking. The same is true with Palladium XP emulation and the Rapid Prototyping Platform, where we are using the same front end and the same flow. To validate that the final FPGA prototyping netlist is functionally correct was traditionally a time-consuming issue. In the System Development Suite you can bring the netlist back to Palladium for verification where you have great debugging.

Q: Finally, any predictions for 2012? Is this the year of the move from RTL to TLM?

A: In 2012 I think we will make significant steps towards that. We are working towards using the same architectural intent for implementation and software enablement and verification. I think we'll see more hybrid approaches where hardware-accurate RTL in an emulator or rapid prototyping system is executed along with TLM models. Will we completely get there [TLM] in 2012 and be done with it? Probably not, but I think we will make significant progress.

Richard Goering

Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

rgoering — Thu, 19 Jan 2012 14:00:00 GMT

Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed-signal simulation. A recently archived Cadence webinar showed how this can be done using a mixed-signal parasitic flow, assertions, and low-power verification.

The webinar, titled "Advanced Technology to Verify Complex Mixed-Signal Designs," was presented by Prabal Bhattacharya, simulation architect at Cadence. It was so full of information that I'll save an overview of power-aware mixed-signal simulation for a follow-up blog post. (Separately, Bhattacharya co-authored a detailed article about mixed-signal assertions for EE Times last year).

Introducing the webinar, Bhattacharya noted that traditional verification approaches based on SPICE and Verilog resulted in "limited channels of communication" between analog and digital teams. "Mixed signal has evolved to the point where you have continuous time domain and discrete time domain objects that interact with and influence each other," he said. He pointed to a simple model in which a voltage equation is driven by a variable that is set by a logic event. A true mixed-signal simulator must "play across" analog and digital domains, he said.

Bhattacharya showed the mixed-signal functional verification "landscape" shown below. On the left side, in the Cadence Virtuoso custom/analog environment, users design schematics, write analog behavioral models and wreal models, and create analog-centric testbenches. On the right side, users of the Cadence Incisive verification platform use methodologies such as metric-driven verification (MDV) and the Universal Verification Methodology (UVM) to provide chip-level verification. "You want to reuse all the things you've done in your Virtuoso environment and hand these off to Incisive by making minimal changes," he noted.

Next Bhattacharya discussed a mixed-signal parasitic flow. Following a top-level simulation in Virtuoso AMS Designer, the analog designers create blocks with schematics, run layout and extraction, and generate Standard Parasitic Exchange Format (SDEF) and/or Detailed Standard Parasitic Format (DSPF) files. Digital block creation, on the other hand, uses RTL coding and generates Standard Delay Format (SDF) files. Bhattacharya showed how analog and digital domains come together through logic-to-electrical and electrical-to-logic "connect modules" that are automatically inserted by the simulator. Then AMS Designer can run a mixed-signal parasitic simulation.

Using Analog/Mixed-Signal Assertions

Assertion-based verification is very familiar in the digital world, but not among analog designers, Bhattacharya said. But wait - analog designers may not use the word "assertion," but they do some things that are similar. These include HSPICE .measure statements, Spectre assert device statements, UltraSim device checks, and behavioral monitoring code in Verilog-AMS. These are all fine at the pure analog block level, but they don't convey meaningful information to digital verification teams.

What's better, Bhattacharya said, is a standard language such as Property Specification Language (PSL) that can be used in both the analog and digital domains. While PSL has primarily been applied to digital logic, he showed how it can be extended to cover mixed-signal expressions with voltage and current. For example, you could write an assertion that says that at the next clock cycle, voltage must be positive at the positive edge of the clock. "When I ship a block to the digital integrator, there is a person there who also uses PSL and can see what I was doing in my pure analog world," Bhattacharya said.

What about System Verilog assertions? There is currently no SystemVerilog-AMS specification, but you can bring real number values into SystemVerilog assertions, Bhattacharya noted. A DAC output could go through an electrical-to-real conversion and come into a SystemVerilog testbench as a real number. Further, an "analog value fetch" capability can be used with Verilog, SystemVerilog or VHDL, among other languages, to bring in analog quantities including voltage, current, power, and device and netlist parameters as real number values.

Bhattacharya concluded this portion of the webinar by showing an assertion browser and comparing it to a waveform display. "You be the judge in whether you want to do this [assertions] or go back to eyeballing waveforms," he said.

You can access the archived webinar here. It's available free to members of the Cadence Community -- quick and easy signup if you're not.

Richard Goering

“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language

rgoering — Tue, 17 Jan 2012 14:00:00 GMT

The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book authored primarily by Cadence R&D experts, titled Advanced Verification Topics, shows how to use metric-driven verification (MDV) and UVM with mixed-signal and low-power designs as well as multi-language verification environments and acceleration.

In 2010 Cadence published A Practical Guide to Adopting the Universal Verification Methodology (UVM), a comprehensive guidebook to UVM. So why write an "advanced topics" book now? Adam Sherer, product marketing director at Cadence and author of the new book's preface, told me that "as we dive below 40nm and into advanced nodes, it's not just a digital world any more. Customers have mixed-signal in there, they need to move up to TLM to handle complexity, and they need MDV." Further, as he pointedly noted, customers need to do some advanced power management at advanced nodes or the silicon will melt.

"The book is for advanced verification engineers and engineering managers who are trying to decide what to tackle next, and want to know how they can improve their productivity by taking a step beyond UVM," Sherer said. He noted that the new book assumes some knowledge of UVM, and if readers don't have that, A Practical Guide to Adopting the Universal Verification Methodology is a great place to start.

The new book discusses extensions to UVM, or "specializations," that are not yet part of the Accellera Systems Initiative standard. As the preface notes, UVM provides a "foundation for specialization," such as extensions needed to support acceleration. But it also notes that specializations built on standards must use open source code and open documentation. That's been done with Advanced Verification Topics.

Metric-Driven Verification and UVM

The first chapter of the book provides a basic overview of MDV, which uses verification planning and coverage metrics to evaluate and guide the verification process. It's a natural complement to UVM, Sherer noted. While UVM helps engineers build reusable tests and test sequences, it can't assess the value of the tests with respect to the verification plan and verification closure. That's where MDV comes in. It helps ensure adequate coverage, measures progress against the verification plan, and ultimately provides meaningful answers to the biggest of all verification questions, "am I done yet?" Other chapters in Advanced Verification Topics are as follows:

UVM and Metric-Driven Verification for Mixed-Signal. This chapter explains why MDV should be used for analog, discusses analog verification planning, and shows how to construct a UVM-MS (UVM-Mixed Signal) verification environment. It describes coverage, assertions, analog model creation, and using UVM-MS verification blocks.
Low Power Verification with the UVM. This chapter presents low-power verification challenges, describes power-aware verification planning, and shows how to configure a power-aware UVM environment.
Multi-Language UVM. This chapter shows how to create UVM Verification Components, called UVCs, that work in environments with more than one language. It provides details about the use of UVM SystemVerilog with the e language and SystemC.
Developing Acceleratable UVCs. Standard UVCs are not architected for acceleration. This chapter presents an approach to UVCs that reuses the stimulus defined in the UVM simulation environment, communicates using the Accellera Systems Initiative SCE-MI standard, and supplies data for MDV.

Advanced Verification Topics is co-authored by Bishnupriya Bhattacharya, John Decker, Gary Hall, Nick Heaton, Yaron Kashai, Neyaz Khan, Zeev Kirshenbaum, and Efrat Shneydor. All work for Cadence except Neyaz Khan, senior scientist at Maxim Integrated Products. The book is available from Amazon. Further information and a preview are available at the Cadence web site.

Richard Goering

Update on OrCAD Free and Paid “Apps” – What is Available Now

rgoering — Mon, 16 Jan 2012 14:00:00 GMT

Last year Cadence announced the OrCAD Capture Marketplace, a web-based capability within the OrCAD Capture environment that provides an on-line store with free and paid plug-in tools, or "apps." Since then the list of available apps for OrCAD Capture and OrCAD PCB Editor has grown to 22, and a free trial period is available for most of the paid apps.

Apps provide a new way to bring new functionality to PCB designers. They're available instantly -- no need to wait for the next software release. You select only the features you need, and you don't have to pay for new capabilities you don't need. And, over time, a community will emerge in which apps will come from a variety of sources.

Accessing an app is as easy as buying or downloading any on-line product (see below). Most paid apps, such as SymbolGen shown below, let you either buy the app outright or click "trial" to give it a test drive for free. If you decide to purchase the app after the trial period, a new app installer is downloaded to turn the app on permanently.

A recent blog post by Jerry Grzenia provides a step-by-step guide on how to access apps from the OrCAD Capture environment. Below is a list of free and paid apps, with free trial periods noted for the paid apps. You need OrCAD version 16.5 or above to use them.

Free Capture Apps

Capture Cached Object Reporting -- Reports out-of-date cached objects in the active Capture design
Capture INI Manager -- Framework for manipulating the Capture INI file
CIPinCIS -- Instant access to search and download component data for millions of parts without having to leave OrCAD Capture
Customize Page on Creation -- Pre-defines automatic callback procedures to customize schematic page creation and attribute
Extended Preferences Dialog -- Provides a GUI for modifying several additional application settings available in OrCAD Capture
Find and Replace Text -- Searches for and replaces text globally in a Capture design
Intelligent PDF -- Shares design intent with intelligent PDF generation for OrCAD
Locked Object Reporter -- Identifies and reports locked objects in the currently active Capture design
Show Open Libraries and Designs -- Lists all open libraries and designs currently active in Capture

Paid Capture Apps

CircuitFit ($499 - free 15 day trial) -- Performs early fit studies at the schematic level before you commit to placement
CIS Quick Start ($99 - no trial) -- Creates a shared, searchable component database for OrCAD Capture CIS in minutes, including a 1000 part starter library
Find in Design ($99 -free 15 day trial) -- Quickly search for common values, like part numbers, across multiple schematics and projects
Status Display Highlight Property ($99 -free 15 day trial) - Helps avoid errors with fully customizable visual indicators of part properties like production status and value
SymbolGen ($999 - free 7 day trial) -- Automated symbol generation tool using advanced PDF datasheet extraction technology
Testpoint Annotation ($99 - free 15 day trial) - Enables synchronization of test points placed in the PCB to nets in the Schematic

Free PCB Editor App

nsWare ShapeUtils -- Free utility to help with shape creation and editing in PCB Editor

Paid PCB Editor Apps

FloWare Cross Section ($980 - free 15 day trial) -- Creates a dynamic table of the design stackup
FloWare LabelTune ($980 - free 30 day trial) -- Automatically adjusts PCB Editor RefDes labels to match part orientation and size
FloWare PCB Panelization ($3500 - free 10 day trial) -- FloWare Module for Cadence Allegro and OrCAD PCB Editor to generate a fabrication panel
nsWare Automatic Artwork Film Setup ($100 - no trial) -- Create artwork (Gerber) film setup in seconds
nsWare PDF Generator ($250 - no trial) -- Create a complete PDF document set for your PCB Design in just seconds
nsWare Planar transformer Generator ($250 - no trial) -- Dramatically decrease the time to create planar transformers in PCB Editor

That's quite a list, and it will only grow over time. Happy designing!

Richard Goering

CDNLive! Silicon Valley – Agenda Set, Registration Open, $99 Deal

rgoering — Thu, 12 Jan 2012 14:00:00 GMT

CDNLive! Silicon Valley, the Cadence user conference for the U.S., is set for San Jose, California March 13-14 at the DoubleTree Hotel. An agenda and registration information are now available on line, and there's a special "early bird" $99 registration deal if you sign up before January 27.

So why attend CDNLive!? Because whatever design and verification work you do, CDNLive! Silicon Valley will help you do it better. This year's conference features over 60 papers that detail user experiences and offer helpful design tips. It also includes interactive "techtorials," a keynote speaker to be identified later, and a Designer Expo showcasing a number of partner providers. There will be many opportunities for networking with peers.

The first day of the conference, Tuesday March 13, features 40 papers divided into 8 tracks, including mixed-signal/low power, custom, verification, SoC/IP, system/software, system verification, and high performance. Of these papers, 32 will be given by user companies or ecosystem partners, and 8 by Cadence. Detailed abstracts for most of these papers are available on line. The day will end with a partner reception and expo.

Wednesday, March 14 is a longer day with 52 papers, of which 34 come from users or partners. Wednesday's tracks are mixed-signal/low power, custom, verification, PCB, system/software, system verification, and "special topics."

Registration gets you attendance at keynotes, access to Cadence R&D and technology experts, entry to all technical sessions, access to the Designer Expo, lunches and coffee breaks, and validated self-parking at the DoubleTree. The conference fee is $199 after the "early bird" special expires January 27.

Meanwhile, CDNLive! EMEA will be held in Munich, Germany May 14-16. Further information is available here.

Richard Goering

Webinar Report: Solving Mixed-Signal Power Grid Challenges

rgoering — Wed, 11 Jan 2012 14:00:00 GMT

Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even for advanced-node, mixed-signal systems on chip (SoCs) with hundreds of millions of transistors.

The webinar is titled "Power Integrity Challenges in Mixed-Signal Designs," and is presented by Harish Kriplani, R&D group director at Cadence. Topics include static and dynamic estimation, simulation methodologies, electromigration rules, hierarchical analysis, "what if" rail analysis, and IC chip/package co-design.

Kriplani started by noting the complexity of advanced-node chips that may have hundreds of millions of transistors and multiple power domains. This, he said, creates a need for hierarchical design, in which you analyze a block and create an abstracted view to use at the next level. He also stressed the importance of early power planning, allowing designers to make "aggressive changes" as early as possible.

A mixed-signal, IR drop and electromigration flow is shown at right. Based on the Cadence Virtuoso platform, this flow includes layout-versus-schematic (LVS) and the extraction of signal and power rail parasitics. It includes SPICE or Fast SPICE circuit simulation and analysis, and makes it possible to graphically display results for easier debugging. Finally, it can create an abstract model with a "power grid view" for analysis at the next level of hierarchy.

Following are some of the issues addressed in the webinar.

Static and Dynamic Estimation

Most webinar attendees were probably familiar with dynamic current estimation, which is really just time-domain analysis in SPICE or Fast SPICE. Static estimation, while much faster, is not as widely known in the analog/mixed-signal world. Here, you partition a circuit and identify logic gates or cells based on pattern recognition. You propagate switching activity through the circuit, or a user-specified power-per-cell, to capture an average switching rate. Using both of these methods can be very powerful - and the static approach may be the only choice for large designs.

Simulate Netlist and P/G Parasitics Together - or Separately?

For IR drop/electromigration analysis, the most accurate approach is to simulate the netlist and the power/ground parasitics together in SPICE or Fast SPICE. This is slow. An alternative is a two-part methodology in which you first simulate the netlist assuming ideal power/ground nets, and then solve the power and ground grids with a separate solver. Kriplani showed how to use these approaches and noted that results from both methods correlate to within 10 percent.

Using Block Abstractions with Power Grid Views

From a hierarchical perspective, you want to analyze a block and create an abstract model of the block that can be brought into full-chip power integrity simulation. Kriplani showed how do this by creating a "power grid view" that includes interfaces and ports, internal transistors, decoupling capacitors, and static or dynamic current distributions. The result: "when you solve the system you are essentially doing a flat analysis."

IR Drop Impact on Circuit Behavior

IR drop can affect circuit behavior significantly. In a digital design, this can be understood by bringing IR drop information into a digital timing tool. For small custom designs, you can simulate the netlist with the power grid parasitics. For larger designers, you can estimate block boundary conditions from a full chip simulation run, and resimulate selected blocks with netlist and grid parasitics.

"What If" Rail Analysis

What-if analysis can be employed for any design that has not gone through full optimization. What-if sensitivity analysis highlights areas where the power grid can be optimized for IR drop. What-if analyses can be used for scaling resistance, capacitance, and currents to understand impacts on IR drop.

Chip-Package Co-Design

If you combine a package with high inductance, a chip with high capacitance, and a power grid designed for low resistance, oscillation may result. Thus, a chip-package resonance analysis is needed. I/O noise analysis is also important.

Cadence Power Integrity Analysis Solution

Only at the end of the webinar did Kriplani provide details about the Cadence power integrity analysis solution. On the digital (Encounter) side, it includes the Encounter Power System (EPS), which can provide full-chip static and dynamic analysis. On the custom/analog (Virtuoso) side, it includes the Virtuoso Power System (VPS), which provides static and dynamic transistor-level analysis.

In a demo, product engineer Rose Li showed how engineers can use VPS to simulate and analyze a custom/analog block and generate a power grid view. She showed how this view can be brought into EPS for a full-chip analysis.

For more details, you'll need to view the webinar yourself. It's available free to members of the Cadence Community - quick and easy signup if you're not. You can see a list of all archived Cadence webinars here.

Richard Goering

Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs

rgoering — Mon, 09 Jan 2012 14:00:00 GMT

Memory is an important part of virtually every electronic system, yet it's increasingly becoming a performance bottleneck. The latest ONFi 3.0 (Open NAND Flash Interface) specification promises to ease this bottleneck for nonvolatile memory. But silicon IP support is needed to facilitate adoption, and Cadence is stepping forward today (Jan. 9, 2012) with the first integrated ONFi 3.0 controller and PHY IP solution. Here's some background on ONFi 3.0 and its importance to system-on-chip (SoC) designers.

While NAND flash is increasingly important in consumer and computing applications, before 2006 there was no standard to help designers integrate NAND flash components with SoC designs. Bob Pierce, senior technical marketing manager at Cadence, noted that SoC designers used asynchronous interfaces with proprietary timing. In 2006 the ONFi working group formed and developed ONFi 1.0, which was basically an asynchronous interface with standardized timing.

In 2008 the working group published ONFi 2.0, which is a dual data rate (DDR) synchronous interface. It delivers speeds up to 200 MT/second. The ONFi 2.1 specification, which followed in 2009, added some new features, and later that year came ONFi 2.2, which allowed more efficient operation with logic unit number (LUN) reset and enhanced page register clear. This is the version most manufacturers are shipping today. You can read a detailed specification history and download the specifications from the ONFi web site.

Boosting Performance

The big difference with ONFi 3.0, published March 2011, is performance - it pushes data transfer rates to 400 MT/second, doubling that of ONFi 2.2. This speed is made possible by a bidirectional source-synchronous DQS and scalable I/O interface. In addition to getting better performance, designers can reduce the number of channels.

The following chart provides other comparisons between ONFi 3.0 and ONFi 2.2. In ONFi 3.0, the 1.8 I/O voltage and the on-die termination both help reduce power. Volume addressing is a virtual addressing scheme that can reduce the number of chip enable pins. A recent ONFi 2.3 spec also includes this scheme.

ONFi 3.0 provides backwards compatibility to previous specifications, and does not require any re-qualification of drivers. As Pierce noted, ONFi 3.0 will be especially attractive for designs that use multiple channels.

Integrated IP

Denali Software, acquired by Cadence in 2010, was the first IP provider to support ONFi 1.0. Now, Pierce observed, Cadence is the first provider to offer an integrated solution with the controller IP, PHY IP, firmware, memory models, and verification IP. An integrated controller and PHY solution are important because the interaction between the two is extremely complex, he noted. The Cadence NAND solution for ONFi 3.0 is shown below.

The Cadence ONFi 3.0 solution includes chip-enable interleaving, configurable error correction, hardware acceleration of key features, and LUN and chip enable operation. It also supports Toggle 2.0, an alternative specification that provides a "non-clocked" DDR capability by doing transfers on strobes. Additionally, the Cadence solution supports ONFi 2.3 and is backward-compatible with all previous ONFi and Toggle specifications.

Significantly, the announcement is taking place this week at the Storage Visions conference in Las Vegas, where Cadence, for the first time, is a conference sponsor. It's more evidence of the increasing emphasis that Cadence is placing on memory IP.

For further insights into ONFi 3.0, see Steve Leibson's Denali Memory Report blog.

Richard Goering

The Denali Memory Report has Returned!

rgoering — Thu, 05 Jan 2012 23:00:00 GMT

For more than a decade, the Denali Memory Report has been an authoritative source of information about business and technology trends in semiconductor memory and storage. The report was published by Denali Software, which was acquired by Cadence in 2010. Now the report has returned as the Denali Memory Report by Cadence, a blog authored by Steve Leibson, marketing director at Cadence.

The report will cover memory market news, market trends, products and product strategies of memory vendors, and alliances and industry consortia. The first posting, dated Jan. 5, reports an announcement by Elpida that it has started shipping samples of 4GBit SDRAMs with both wide I/O and LPDDR3 interfaces. Both types of interfaces are expected to have a strong impact on the DRAM market this year, and the Elpida announcement will help push things forward.

Steve will continue to write EDA Insider, a blog he started in 2010. EDA Insider had over 500 posts last year. A Jan. 3 posting lists the 13 most popular EDA Insider blogs of 2011.

In my view, the return of the Denali Memory Report is one more indication of the strong focus that Cadence is placing on the memory market. Last year Cadence rolled out an IP strategy in which memory (DRAM) and storage (NAND flash) controller IP takes center stage. Also last year, Cadence announced the first DDR4 IP solution (including controller, PHY, and memory models) and the first wide I/O memory controller IP. Next week Cadence will exhibit at the Storage Visions conference in Las Vegas and will be, for the first time, a sponsor.

Memory is a vital part of any electronic system architecture, and it must be considered early and often by designers. If you're involved in the design of ICs or SoCs that have interfaces to memory, or simply want to keep up with trends in memory and storage, don't forget to read the Denali Memory Report by Cadence.

Richard Goering

User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

rgoering — Thu, 05 Jan 2012 14:00:00 GMT

Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using the Common Power Format (CPF). The new flow provides many advantages compared to the traditional bottom-up, single-mode synthesis approach.

This was one of three user presentations at the event, which also featured a panel session involving the presenters. All of the user presentations focused on low-power design, and power was a prominent topic at the panel discussion. A previous blog post includes a report of the panel.

In a memory controller, Borbely-Bartis noted, sub-modules may have different timing requirements, and there could be multiple power domains. With bottom-up synthesis, however, sub-module I/O delay is budgeted for the worse case, and as a result some paths are over-constrained. Single-mode synthesis constrains the top level in order to satisfy the worst-case mode. Power structures including isolation cells (ISO) are added later, power shutoff (PSO) simulation is delayed until the netlist is available, and design for test (DFT) structures are also added late in the flow.

The traditional flow looks like this, where A1 and A2 are sub-modules and LEC is logic equivalence checking:

The new, multi-mode flow (below) starts with a CPF file that describes power intent and a power-aware simulation. Top-down synthesis makes module-level standard delay format (SDF) files unnecessary. The top level is constrained for each mode, and power structures and DFT are added during synthesis. "We provide multiple SDC [standard design constraint] files for the different modes," Borbely-Bartis said.

Borbely-Bartis showed how the CPF file defines libraries and cells, creates power domains and modes, establishes isolation rules, and specifies power management cells including those for ISO and PSO. He noted that the CPF file allows for RTL PSO simulation, permitting early detection of possible power problems. When a PSO signal is asserted, the signals inside a shut-off domain are automatically forced to "X" (unknown) states. Thus, no testbench modification is needed for PSO support.

Each functional mode is described in a separate SDC file. There are also dedicated modes for scan and memory built-in self test (BIST).

As a result of the new flow, the design is not over-constrained, and ISO and PSO cells are automatically inserted. The final LEC is automated and driven by the CPF file, making LEC power-aware. In the old flow, Borbely-Bartis noted, die size may increase and overall timing may suffer.

Borbely-Bartis uses tools including the Cadence Encounter RTL Compiler, Conformal LEC, Conformal LP, Incisive simulation, and the Encounter Digital Implementation System. All these tools read CPF. PSO simulation with RTL, he noted, "allows early detection of most power issues. It also allows us to do more testing. Whatever you find, fixing RTL is much easier than reporting ECOs later."

Richard Goering

All Things Analog – Video Interviews with Experts

rgoering — Wed, 04 Jan 2012 14:00:00 GMT

John Pierce, product marketing director at Cadence, recently sat down with several analog/mixed-signal design and verification experts for "All Things Analog" video interviews. These short (8-11 minute) video clips offer some good insights into analog verification and simulation, PLL design, low-power design, and mixed-signal systems-on-chip (SoCs). All are now available for viewing on the Cadence Design Systems YouTube channel, as noted below.

In the first interview below, Pierce talked to Ken Kundert, president of Designer's Guide Consulting, and Henry Chang, vice-president at the same company. Kundert and Chang both previously worked at Cadence, and they talked about their move to analog/mixed-signal verification consulting. Chang, who wrote a book on digital verification, noted that the techniques he described in the 1990s are "now becoming applicable in the analog world." Kundert and Chang talked about the challenges of simulating circuits such as audio codecs and sigma-delta converters.

To view the video, open the icon below or click here.

In the second All Things Analog video, Pierce talked to Nandu Bhagwan, president and CEO of GHz Circuits Inc. This interview focuses on the challenges of PLL design and simulation. Bhagwan described how he uses abstraction to run simulations in a reasonable period of time.

To view the video, open the icon below or click here.

In the third video, Pierce talked to Dave Stone, vice president of marketing and sales at Triune Systems, and Ross Teggatz, president and founder of Triune Systems. This company is a fabless semiconductor supplier focusing on "green" solutions, so this conversation naturally turned to low-power design. Stone and Teggatz also discussed the complexity of mixed-signal SoCs compared to older analog designs.

To view the video, open the icon below or click here.

For more information about Triune and a solar power management chip they developed, see my previous blog post or check out a Cadence webinar that described the design challenges behind this innovative chip.

Analog/mixed-signal design and verification is sure to be a big topic in 2012. These videos offer some food for thought to help get the discussion going.

Richard Goering

2011 EDA Standards Update and 2012 Forecast

rgoering — Wed, 21 Dec 2011 14:00:00 GMT

As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive year for EDA standards developments and 2012 is looking promising as well. This blog post summarizes some key developments.

Perhaps the biggest standards news of the year was the merger of Accellera and the Open SystemC Initiative (OSCI) into the Accellera Systems Initiative, completed Dec. 5, 2011. This follows the 2010 merger of the SPIRIT Consortium into Accellera. As I noted in a blog post earlier this month, the stage is now set for a unified, front-end EDA standards effort that cuts across multiple levels of abstraction. Looking forward to 2012, there are many opportunities for convergence among standards efforts such as Accellera's Universal Verification Methodology (UVM), IP-XACT from the SPIRIT Consortium, and OSCI SystemC and Transaction-Level Modeling (TLM-2.0).

While the Accellera Systems Initiative concentrates on front-end standards, the Silicon Integration Initiative (Si2) is traditionally focused more on the back end. A major Si2 development in 2011 was the release of Common Power Format (CPF) 2.0, an update that facilitates interoperability between CPF and the IEEE 1801 Unified Power Format (UPF), and the contribution of CPF 2.0 to IEEE 1801. Cadence, the originator of CPF, is now actively participating in IEEE 1801. An October blog post has further information about Si2's work in power standards.

Here are updates on some other key standards efforts (not necessarily in order of importance). Cadence is placing a strong priority on standards and is actively involved in most of the efforts listed below. Thanks to various committee chairpersons for helping with these updates.

ACCELLERA SYSTEMS INITIATIVE

UVM - On Feb. 18, 2011, Accellera approved the long-awaited UVM 1.0 as a new industry standard. Currently based on SystemVerilog, UVM provides a standard methodology so that verification IP and testbenches can be reusable and interoperable in different simulation environments. A bug fix release, UVM 1.1, was subsequently issued, and a more substantial new release, UVM 1.2, is expected in 2012.

SystemC - Before the merger with Accellera, OSCI working groups made continued progress in 2011 in defining a synthesis subset, analog/mixed-signal extensions, and model configuration and control. While the SystemC language itself is now under IEEE 1666, OSCI worked on a proof-of-concept reference model. Six OSCI SystemC working groups are now part of the Accellera Systems Initiative.

Unified Coverage Interoperability Standard (UCIS) - In 2011, the UCIS committee completed the technical work for a version 1.0 draft of a standard that will foster interoperability between verification coverage metrics from different sources. The standard is heading for approval in early 2012.

Standard Co-Emulation Modeling Interface (SCE-MI) - Accellera released version 2.1 of the SCE-MI standard, which added a "pipes" interface to the previous methods of communicating between software execution and hardware acceleration. Additional capabilities are planned for 2012 including SystemC and SystemVerilog interfaces.

IP-XACT - This standard provides metadata that documents the characteristics of silicon IP. In 2011 the working group captured new requirements and defined a process for the release of standard extensions.

IEEE WORKING GROUPS

IEEE 1666 (SystemC) - The first IEEE revision of SystemC in six years, IEEE 1666-2011, was released in November. The language reference manual includes the TLM modeling specifications from OSCI; it also adds process control statements, based on technology developed by Cadence.

IEEE 1800 (SystemVerilog) - A new version of the SystemVerilog standard is expected in 2012.

IEEE 1801 (Unified Power Format) - As noted above, Cadence has joined this working group, which now has access to CPF 2.0. A new revision, IEEE1801-2012, is planned for 2012. Looking further out, a "UPF 3.0" release is expected to include concepts from OpenLPM and CPF.

IEEE 1647 (e language) - IEEE 1647-2011 was published in August 2011 with a number of language updates. The working group is awaiting feedback on the standard and will start an open period for new contributions in mid-2012.

IEEE 1734 (IP quality) - The IEEE approved IEEE 1734-2011, a standard for IP quality, in June and released it in September 2011. The group is looking for industry feedback before undertaking any revisions or enhancements.

SILICON INTEGRATION INITIATIVE

OpenAccess Coalition - In 2011, a new OpenAccess release included support for 28nm constraints and compressed databases. OpenAccess scripting language bindings were released. A 2012 OpenAccess release will include scratch designs and other functionality and performance improvements.

DFM Coalition - The OpenDFM 1.1 physical verification standard was released in 2011, including electro-static discharge checks, latch-up checks, edge checks, and new targeting functions for manufacturability. In 2012, OpenDFM 2.x will include DRC+ and other enhancements.

OpenPDK (Process Design Kits) - Work has started on the Open Process Specification, which will include a symbol standard, a design parameter standard, a callback standard, and other design rules.

Low Power Coalition (LPC) - CPF 2.0, released in 2011, facilitates interoperability with IEEE 1801. Updated power modeling standards are expected in 2012.

Open3D (3D-ICs) - This new effort formed working groups in 2011 and is expected to release standards in 2012 defining power distribution network across the die of a 3D stack, thermal design and analysis of an entire 3D stack, and expression of design constraints into and out of the pathfinding and floorplanning phases of the design process.

It's a long list and it's not a complete list - many EDA standards efforts are ongoing. Here's a big end-of-year "thank you" to all those individuals who are donating their time to making these standards happen.

Richard Goering

Synthesis User Panel: Power Dominates Front End Design

rgoering — Mon, 19 Dec 2011 14:00:00 GMT

What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list.

The panel included three user presenters, an ARM executive, and a Cadence R&D representative. Each of the three user presenters had previously given a separate presentation. Panelists were as follows, shown left to right in the photo below:

John Heinlein, vice president of marketing, ARM Physical IP division
Murali Natarajan, senior physical design manager, Marvell
Simon Wong, project manager, OmniVision
Laszlo Borbely-Bartis, staff design engineer, Micron
Jean-Charles Giomi, R&D vice president, Cadence

The panel was moderated by Steve Carlson, engineering group director for front-end design at Cadence. Prior to the panel, Adel Khouja of Cadence talked about modern synthesis trends and challenges, as reported in my previous blog post.

Power on Top

Carlson started the panel discussion by asking how design methodologies will change in the next 2-3 years. Given that every user presentation focused on low power design, as did Heinlein's presentation, the answers were not surprising.

"Power is pervasive in everything we do," Heinlein said. "There's a lot of work targeting leakage and dynamic power, and we're seeing power management baked into designs in places where it wasn't present before." In particular, he noted, clock power has become a serious problem.

"I agree that power is the main problem in design," Natarajan said. One trend he's seeing is the move to 2.5D and 3D die stacking. However, tool support is just getting started, he said.

In consumer electronics, Wong noted, time-to-market is shrinking just as complexity is going up. Power is a major factor in that complexity. "We have to use multiple power modes and multiple power domains," he said. Borbely-Bartis commented that power-efficient designs are becoming more and more important, and time-to-market is shrinking, leading to the increasing use of third-party IP. "In the long term," he added, "I would not be surprised if the RTL is generated by tools."

Giomi noted that power, performance and area (PPA) will continue to be a focus for front-end tools. Trends over the next couple of years include increasing physical awareness, and a growing need to handle greater complexity and capacity.

Will Front End Design Disappear?

Wong made the point that front-end design is experiencing a "split." He observed that part of it is being integrated into the design flow on the RTL side, and another part is becoming more integrated with the back end. "When we do synthesis with multiple power modes and a lot of other constraints, we are actually saving time on the back end," he said.

Carlson picked up on this theme by asking whether RTL synthesis will be absorbed into the back end, resulting in an RTL-to-GDSII tool, or whether high-level synthesis will replace RTL synthesis. Several panelists observed that different design sizes and styles will have different requirements, with some chips or blocks calling for physical-aware synthesis while others do not.

Wong said that designers are doing a lot more low-power checking and timing checking, thus saving time in the front end. "On small size designs we see the front end starting to disappear a little bit in terms of schedule and importance," he observed. He also noted that "we try to cut turnaround time between the front end and the back end. If we have to go back to the designer to change RTL code, that is a nightmare."

"In the early phases of design you need a very quick turnaround," Borbely-Bartis said. "For production, you should provide as much physical information as you can. I would see synthesis as part of place and route."

Carlson asked how many audience members think synthesis will become part of the physical design flow. Around 30-40% raised their hands. He asked how many think synthesis will be more closely tied to C language modeling and verification. Perhaps 10% raised their hands. "I don't think these are mutually exclusive," Heinlein said. "Everybody has to care about physical issues."

Questions and Concerns

Several audience members offered questions or comments during the panel. One asked whether SystemVerilog is being used for RTL design, and Giomi noted that Cadence is seeing increasing use of SystemVerilog for this purpose. Another commented that the most important aspect of synthesis is a fast turnaround time.

Another audience member asked if there's any way to qualify, or get a "stamp of approval," that third-party IP is good. "I'm on the GSA working group on that topic," Heinlein said. "The simple answer is that there isn't a standard."

Powerful Presentations

The panelists had previously offered the following presentations:

"ARM-based SoCs with High Performance and Low Power" by John Heinlein, ARM. This presentation provided an update on ARM processors including the Cortex-A7, Mali GPU, and Processor Optimization Packs.
"Delivering a Consumer Video Bridge ASIC Using the Cadence Low-Power and DFT-Enabled Synthesis" by Simon Wong, OmniVision. This presentation showed how a small group of people on a very tight time schedule navigated a successful tapeout.
"Accelerating Advanced Lower Power Design using Unified Power Intent," Murali Natarajan, Marvell. This presentation showed how and why designers moved from the Unified Power Format (UPF) to the Common Power Format (CPF).
"Concurrent Multi-Mode and Low Power Optimization Synthesis Flow using CPF," Laszlo Borbely-Bartis, Micron. A new synthesis flow starts with a CPF file and power-aware simulation, avoiding over-constraining the design and allowing more automation of low-power design.

The event also included technology demonstrations, lunch, and a reception with Cadence R&D. All in all, it was a very powerful half-day event for users of RTL synthesis tools.

Richard Goering

An Update on the JEDEC Wide I/O Standard for 3D-ICs

rgoering — Thu, 15 Dec 2011 14:00:00 GMT

One of the big advantages of 3D-ICs with through-silicon vias (TSVs) is the potential for much faster memory bandwidth compared to conventional 2D ICs. That's why the emerging JEDEC wide I/O mobile DRAM memory standard, which takes full advantage of 3D die stacking to provide significant power and performance gains, is a key driver for the move to 3D-ICs. A timely update on wide I/O was presented Dec. 12 at the Global Semiconductor Alliance (GSA) 3D-IC Working Group meeting in Santa Clara, California.

I say "timely" because the speaker, Ken Shoemaker, vice-chair of the JEDEC JC-42.6 committee, noted that the initial wide I/O specification has been approved by the JEDEC board of directors and "should be published any day now." Shoemaker provided some background about the specification, detailed what it does and doesn't cover, and talked about thermal and test challenges and solutions.

JEDEC describes wide I/O as "a breakthrough technology that will meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor. Wide I/O mobile DRAM memory uses chip-level three dimensional (3D) stacking with through silicon via (TSV) interconnects and memory chips directly stacked upon a system on chip (SoC). Wide I/O is particularly suited for applications requiring increased memory bandwidth up to 17GB/second, such as 3D gaming, HD video, simultaneously-running applications, etc."

Wide I/O defines four memory channels each 128 bits wide, providing a 512-bit wide interface to memory. The interface supports a single data rate of 266M transfers/second, and channel bandwidth of 4.26GB/second, or total bandwidth of 17GB/second (up from 12.8GB/second targeted earlier in the standards effort). The goal of wide I/O, Shoemaker noted, is to provide "double the bandwidth at the same power, or cut power in half at the same bandwidth" compared to LPDDR2 and LPDDR3. "It lets you get smaller form factors and lower power, so what's not to like?"

What the Spec Covers

The wide I/O specification defines the logic/memory interface (LMI). Two JEDEC committees have contributed to the wide I/O specification. While the JC-42.6 (low power DRAM) group has focused on functional aspects of the device, the JC-11 (mechanical standardization) group has focused on mechanical aspects of the chip, such as pad dimensions, tolerances and locations. The mechanical interface is called a micropillar gate array (MPGA).

The specification also standardizes the following:

Boundary scan testing for interconnect. Boundary scan logic is integrated into the die for contact and I/O testing, providing full test coverage for MPGA contacts, drivers and receivers.
Post-assembly DRAM testing. This makes it possible to test the DRAM separately from the logic chip it's packaged with. Two methods are provided - direct access via DRAM pins, and electrical connection through GPIO drivers/receivers.
Exact mechanical layout of chip-to-chip interface.
Memory thermal sensor locations for DRAM, to provide reliable operation given thermal gradients introduced by logic chips.

Thermal integrity is obviously a big concern for 3D-ICs, and Shoemaker went into some detail in this area. He explained that the DRAM self-refresh rate varies with temperature, and DRAM chips expect a uniform temperature. However, logic chips generate non-uniform hot spots as various activities take place, such as watching a video. Therefore, the logic chip will determine the temperature delta between the memory hot spot and the location of the thermal sensor on the DRAM. Wide I/O seeks to standardize locations for memory thermal sensors, but the accuracy of the sensor and the algorithm it uses is a proprietary matter.

Here are some more details on the 4-channel LMI:

Each channel includes all control, power and ground signals, and is independently controlled
Each channel has 300 connections, 6 rows by 50 columns
Up to four ranks per channel
1.2V CMOS signal levels
Pad pitch is 40u x 50u. Total LMI dimension is 0.52mm X 5.25mm.

"You have to do the math to figure out how much this is going to change your die area," Shoemaker said.

What the Spec Doesn't Cover

Shoemaker presented a long and important list of items the wide I/O spec does not cover. This includes any internal aspects of the memory chip or memory stack. The spec doesn't mandate the interconnect method between memory and logic chips - it could be face-to-face, side-by-side with interposer, or stacked memory on top of logic. The exact mechanical placement of the interface on the logic or memory chip is up to the designer, although "we presume it's in the center of the memory chip." Dimensions and placement of TSVs are not specified.

Shoemaker also noted that discussions are underway about the next generation of wide I/O. There are proposals for significantly higher bandwidth, and explicit support for 2.5D assembly. There's also a JEDEC High Bandwidth Memory group that is leveraging some of the wide I/O work, but this group is targeting high-performance applications. Wide I/O is more focused on mobile devices and tablets and other power-sensitive applications.

Wide I/O Gets Real

On Dec. 13, at the RTI 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, California, representatives of CEA-LETI and ST-Ericsson described the development of a three-die stack with wide I/O memory and two logic dies. This 3D-IC is the result of collaboration between these two organizations and Cadence, which provided the design tools and the wide I/O controller IP for the project. A previous blog post has details.

In March 2011, Cadence announced the first commercial wide I/O memory controller IP solution. As described in a previous blog post, the Cadence wide I/O offering includes a configurable memory controller, PHY (physical layer), and verification IP. Cadence also provides a comprehensive methodology and tool support for 3D-IC/TSV design, including IC/package co-design, 3D-aware floorplanning and routing, extraction, thermal analysis, test, and custom/analog design as well as digital. That flow is described in a previous blog post.

In summary, wide I/O presents a compelling new technology for a new generation of mobile, high-bandwidth, low-power devices. The emerging JEDEC specification will help drive this technology and bring 3D-ICs with TSVs into the mainstream.

Shoemaker's presentation is available at the GSA web site.

Richard Goering

How Logic Synthesis is Changing

rgoering — Wed, 14 Dec 2011 14:00:00 GMT

You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community Event held at Cadence Dec. 8.

The event included user presentations along with a Q&A panel discussion. I'll have more on that in a later post. This post focuses on a presentation by Adel Khouja, vice-president of R&D at Cadence, titled "Modern Synthesis Trends and Challenges for Today's and Tomorrow's Chip Design."

The talk focused on three trends - physical awareness moving upstream, power analysis and optimization, and increasing capacity requirements. Khouja began by noting that there has traditionally been a "very strong separation" between front-end and back-end design, but this is changing because physically-driven gate-level optimization has become necessary to close timing. Today, he observed, "physical knowledge is permeating logic synthesis" and is even moving up to architectural selection phases.

Physically-Aware Synthesis

Khouja reviewed a number of ways in which front-end design and synthesis can become more physically aware. These include estimating and preventing routing congestion, using physical awareness during design for test (DFT), and restructuring and re-mapping logic based on physical knowledge. Suppose, for example, you want to find the best implementation for a multiplexer. "The point is, this is not a trivial decision, and you would want to base it on physical information," Khouja said.

As for power, Khouja noted that both dynamic and leakage power have been concerns for many years, and neither one is going away - in fact, with process advancements now promising to reduce leakage power, dynamic power is re-emerging as a serious concern. There is also increasing interest in bringing power estimation up to the architectural level, he noted. What won't be changing soon, he said, is the focus on power as something almost as critical, if not more critical, than timing.

Khouja said that a "holistic" approach to power intent specification is vital, so that power intent can be conveyed and optimized throughout the flow. He predicted more cooperation among EDA vendors around the area of power intent.

Capacity has always been a challenge for synthesis, and top-down methodologies have increased memory requirements and run times. Further, some designs are already at the 20-50 million gate equivalent range with future designs surpassing 100 million gates. Controlling capacity and run time "is an exciting area and our team is working on this," Khouja said. One way to improve capacity is through multi-threading and shared memory, and another is distributed processing.

Physical Synthesis or Physically Aware?

An audience member asked if "physically aware" synthesis is the same thing as "physical synthesis." Khouja replied that "physical synthesis is a very vague and broad term. I think we're going beyond that...we're talking about physical aware logic synthesis. We're taking placement, congestion, blockages, and the clock tree, and moving it into the front end. What you're likely to see is really a merging of the front end and the back end over time."

Synthesis is a technology that is absolutely central in the IC design flow. It's good to know that the technology is still evolving and improving.

Richard Goering

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

rgoering — Tue, 13 Dec 2011 14:00:00 GMT

A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and Cadence, which provided the design tools and the wide I/O controller IP for the project.

The project will be described in a paper presented by Pascal Vivet, research engineer at the CEA-LETI research institute, and Vincent Guerin, senior digital design engineer at ST-Ericsson, at the RTI 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, California. This proof-of-concept design is a step forward in several respects:

It's a heterogeneous three-die stack that includes memory and logic (as opposed to memory only). Logic is provided by two identical multi-core systems-on-chip with TSV interconnects.
It uses a wide I/O DRAM interface to boost bandwidth and reduce power.
It employs a novel 3D asynchronous network-on-chip (NoC) architecture developed by ST-Ericsson.
The successful design effort validates the Cadence 3D-IC implementation flow.

The project actually involved three test chips - memory plus logic, two SoCs stacked together, and memory stacked on top of two SoCs. Here's a diagram of the three-die stack. The package is a 12x12 BGA with 581 balls. It includes several thousand micro-bumps and around 2,000 TSVs per SoC. The diagram shows the face-down orientations of the three dies.

Expertise in Three Dimensions

The LETI research institute brought its manufacturing expertise to the project. LETI offers TSV "toolboxes" including via-first, via-middle, and via-last methodologies (via middle was used on the SoCs in this project). LETI has a 300mm 3D manufacturing line and has experience in stacked die implementations.

ST-Ericsson designed the WIOMING SoCs used for this project. These chips include an ARM host CPU, DSP and ASIP engines, and multi-core CPU backplane. ST-Ericsson also developed the 3D asynchronous NoC. (Conceptually, a NoC replaces a fixed bus with a packet-based approach and a layered methodology. NoC implementations have primarily been used with 2D multi-core SoCs).

The thing that's different about this NoC is that it works in three dimensions. Employing fast serial data links and fully asynchronous logic, it achieves 550M transfers/second throughput in the 2D (intra-die) direction, and 200M transfers/second in the 3D (inter-die) direction. Serialization reduces the number of TSVs at the 3D NoC interface. The NoC also provides fault tolerance and supports a design for test (DFT) architecture based on test wrappers.

Wide I/O memory is a new DRAM technology and an emerging JEDEC standard that calls for a 512-bit wide interface and 12.8GB/second bandwidth. In addition to high bandwidth, it promises 2X the power efficiency of LPDDR2 and LPDDR3. Beyond the 12.8 GB/second bandwidth in the initial JEDEC spec, increasing DRAM frequency to 266 MHz and using dual data rate transfers will eventually provide more than 34 GB/second.

The 3D-IC project used the Cadence wide I/O memory controller, introduced in March 2011. This controller IP is fully compliant with the JEDEC wide I/O specification and includes advanced low-power features and memory built-in self test (BIST) tests. Cadence also provides a PHY, verification IP, and memory models.

Design Flow

The 3D-IC project used the Cadence Encounter Digital Implementation System 3D-IC flow, including Encounter Power System, Encounter Timing System, floorplanning, routing, and extraction and analysis. The overall flow was introduced in early 2011 and is described here. The flow makes it possible to automatically create and assign TSVs; floorplan with a knowledge of what's on adjacent dies; perform TSV routing; extract TSVs; and run IR drop analysis on 3D stacks.

The overall message is that wide I/O 3D-IC technology is ready for production, and that heterogeneous die stacks with more than two dies have arrived. The result will be a new generation of low-power, high-performance mobile devices - and given the competitive consumer market, they won't be long in coming.

Richard Goering

For a more detailed view of this development, see Steve Leibson's blog post.

ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

rgoering — Thu, 08 Dec 2011 21:00:00 GMT

In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July. At the recent ARM TechCon conference, attendees heard the story of this development and its challenges in a paper presented by ARM, Cadence and Samsung engineers.

The paper was titled "20nm Logic Test Chip Implementation by Samsung, ARM and Cadence." It was presented by Taejoong Song, principal engineer at Samsung; Imran Iqbal, principal design engineer at ARM; and Bimal Gisuthan, senior applications engineer at Cadence. Proceedings are available to conference attendees at the ARM TechCon web site.

Samsung provided the 20nm high-k metal gate (HKMG) process that was used for the test chip, and Song began the presentation with an overview of the process and its development. Noting that the 20nm process provides both low power and high performance, he noted that it's 15% faster than the Samsung 28LPH process and 35% faster than the Samsung 28LP process. However, there were some process challenges, including short-channel effect, complicated device structures, and self-aligned vias.

The process also posed some design challenges, including aggressive design rules, parasitic variation in process corners, and "harsh" electro-migration. A "pre-emptive" approach to placement and routing was needed, and part of the collaborative effort went into "routing enablement" for 20nm. This enablement included router support for a mix of bidirectional and uni-directional routing, metal pitch rules for preferred and non-preferred directions, and via rules for 20nm.

Stepping Up to nSTEP

Iqbal spoke about nSTEP microcontroller implementation using the Cadence 20nm Silicon Realization flow. He talked about the goals of the three-way collaboration, which were as follows:

Enable a simple ARM core for early 20nm technology demonstrator
Investigate place and route issues
Understand standard cell design trade-offs
Verify functionality of the 20nm process

He also talked about the nSTEP reference system (STEP = System Test Evaluation Platform), nothing that it includes the Cortex-M0 32-bit CPU, two banks of SRAM, and external bus interfaces. It's a good test platform because all it needs are basic standard cells. The 20nm test chip project actually used two variants of nSTEP. The HP (high performance) version used 12-track standard cells and targeted 200MHz, while the HD (high density) version used more aggressive 9-track cells and targeted 100MHz.

Iqbal went into some detail about the floorplan, which was pad-limited with special corner pad spacing. He identified several challenges, including spacing of corner pads, placement of memory macros and endcap cells, and density requirements that called for special filler cells. He also noted that setup time was fairly easy to meet, but designers ended up fixing hold violations at four different corners.

Silicon Realization Flow

Gisuthan provided more information about the design tools used in the test chip effort. He cited the use of the Cadence Encounter RTL Compiler, Incisive Enteprise Simulator, Encounter Digital Implementation System, QRC Extraction, Encounter Timing System, Encounter Power System, and Encounter Test. The design flow looked like this:

"It's the same flow used at 40nm and 32nm, but the difference is that every step of the flow was 20nm aware," Gisuthan said. This includes placement, routing, and clock tree synthesis. One "unique challenge" was power planning. He showed how an aggressive, differential IR drop requirement (25 millivolts) led to a very dense power structure with a power plan that encompassed metal layers 3 through 9. He also described the team's challenges in fixing hold violations with a 150ps margin, and noted that some special delay cells were needed.

Gisuthan also provided an in-depth view of the "routing enablement" for 20nm that Song had noted earlier. "Given so many changes in design rules, it's important for a router to be 20nm ready and to achieve fast automated DRC coverage," he said. "In this respective NanoRoute performed very well." He discussed a couple of rules that caused challenges, including a cluster via rule and a non-preferred direction spacing rule.

"In a short time we were able to achieve two unique implementations of the nSTEP microcontroller," Gisuthan concluded. "We validated the Cadence 20nm digital methodology including Encounter Digital Implementation System implementation and signoff, and tested and validated Samsung libraries. Very strong collaboration between Cadence, ARM and Samsung was a key component of this 20nm success."

Richard Goering

Other blog posts about ARM TechCon 2011 papers:

ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs

ARM TechCon Paper: Why DRAM Latency is Getting Worse

ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development

ARM TechCon Paper: Early Architectural Planning with a Digital Implementation Flow

Archived Webinar: Using Scoreboards With Formal Verification

rgoering — Wed, 07 Dec 2011 14:00:00 GMT

If you've run simulation, you have probably used scoreboards to check that outputs properly match inputs. As revealed in a newly archived webinar, there's an easy way to use scoreboards with formal verification. It requires a slightly different methodology, but it turns out to be a good way to quickly find data transport bugs.

The webinar, titled "Quickly Find Data Transport Bugs with Formal Scoreboarding," was presented Nov. 17, 2011 by Joerg Mueller, solutions engineer at Cadence. It's available on demand to Cadence Community members by registering here.

At the start of the webinar, Mueller noted the "conventional wisdom" that formal verification works for control logic but not at all for datapath. The fallacy, he said, is that people who make that claim aren't distinguishing data transport from data transformation. While data transformation continues to be difficult for formal technology, "data transport is a sweet spot if you apply the right methodology," Mueller said. Scoreboarding is a classical approach to datapath checking, and a modified approach to scoreboarding enables formal tools to find data transport errors.

Formal Scoreboarding

In simulation, a scoreboard samples all input values, stores them in a tracker, and then checks the output for matches of tracked input values. If an output value does not exist in the tracker, there's a bug. At the end of the simulation the tracker should be empty.

While this methodology works well for simulation, it results in too many input values for a formal verification tool. A simulator can handle a flexible variable list, but a formal tool needs a fixed-size list. Thus, the approach described in the webinar tracks symbols rather than values. The tool selects one arbitrary input value, chosen to trigger failures, that is represented as a "symbol." The scoreboard checks the output for matches of the tracked input symbol. One symbol represents all possible values, in all possible locations, under any possible condition.

Mueller showed how this approach can be applied to datapath checking using a liveness check ("what goes in must eventually go out"). Such a check will find data loss and corruption errors, but miss data ordering and creation errors. There are also potential capacity and performance "gotchas" with this kind of check. One solution is parameterization (reduce datapath depth and width) and check reduction (reduce check width).

Sequences of Symbols

Another alternative is to use safety properties instead of liveness properties, and to apply sequences of symbols. Here, you force (constrain) a sequence of input values and check (assert) that the same sequence will occur at the output. Mueller reviewed several different types of sequences. For example, a sequence with two consecutive symbols can find errors due to data loss, manipulation, creation, duplication, or data reordering. This approach "provides all the verification capabilities of a full-fledged simulation style scoreboard, but the formal tool has only to work with a single symbol storage," he said.

Mueller showed how users of the Cadence Incisive verification platform can access these capabilities today with the Incisive Formal Scoreboard, included in the Incisive 10.20 s100 release. It provides datapath checking, including liveness and sequence checks, and it works with both formal and assertion-driven simulation. "Data transport verification is a great target for formal," Mueller concluded.

Richard Goering

Accellera-OSCI Union Completed – What It Means for EDA Standards

rgoering — Mon, 05 Dec 2011 16:27:00 GMT

Two prominent EDA industry standards organizations -- Accellera and the Open SystemC Initiative (OSCI) - announced today (Dec. 5) the completion of their merger under the name "Accellera Systems Initiative." The stage is now set for a unified EDA standards effort that cuts across multiple levels of abstraction, from the SystemC language developed by OSCI to the Verilog, SystemVerilog and VHDL hardware description languages for which Accellera is best known.

The pending merger was announced in June 2011 as a way of uniting front-end IC design standards activities at the systems, software, and RTL levels. It was presented from the start as a merger of equals rather than one organization folding into another. OSCI's five working groups have joined Accellera's seven working groups as equal partners. Shisphal Rawat, Accellera chair before the merger, is the current chair of the Accellera Systems Initiative.

The creation of the Accellera Systems Initiative "creates a single home for front-end EDA and IP standards," said Stan Krolikoski, Accellera Systems Initiative secretary and group director of standards at Cadence. "This will facilitate the exploiting of synergies between standards such as SystemC, UVM and IP-XACT, just to name three, and will also create an infrastructure under which synergistic standards efforts can be done in tight harmony from the beginning."

Synergies and Opportunities

What are some of the possible "synergies" that may arise from the combination of Accellera and OSCI into one organization? The following illustration shows opportunities in three areas:

Synergies and future opportunities. Source: Accellera Systems Initiative

System-Level IP Integration - In 2010 the SPIRIT Consortium, developer of the IP-XACT metadata standard for IP integration, merged into Accellera. Consequently, Accellera is aligning IP-XACT register definitions with the Universal Verification Methodology (UVM). Now, Krolikoski said, there's a possibility of fully bringing SystemC descriptions into the information captured by IP-XACT.
System-Level Verification - UVM has already implemented the OSCI TLM-2.0 (transaction-level modeling) standard. Presently UVM has been defined for SystemVerilog only, but there has also been some user interest in a UVM SystemC capability, as reflected in a "town hall" meeting at the DVCon conference in February. The OSCI Configuration, Control and Inspection (CCI) modeling specification could be a powerful adjunct to a UVM SystemC capability. Finally, the upcoming Unified Coverage Interoperability Standard (UCIS) could be enhanced to work with SystemC.
Mixed-Signal Design and Verification - Verilog-AMS (analog/mixed-signal) and SystemC-AMS standardization efforts have so far been disconnected, but now that both are under one roof, mapping between SystemC-AMS and Verilog-AMS may become possible.

On the organizational level, Krolikoski noted, the Accellera Systems Initiative retains a strong technical chair (Karen Pieper, Tabula), which is not a position that OSCI had. The Accellera Systems Initiative has a Marketing Committee, a capability that OSCI had but Accellera did not. It is chaired by Thomas Li of Springsoft.

The following seven working groups came from Accellera:

Interface Technical Committee - SCE-MI standard for co-emulation and transaction-based acceleration
IP-XACT Working Group -- Metadata standard for IP integration
IP Tagging Technical Committee - Tracking IP throughout development process
Open Verification Library Technical Committee - OVL assertion library
Unified Coverage Interoperability Standard (UCIS) - Verification coverage interoperability
Verification Intellectual Property Technical Committee - Universal Verification Methodology (UVM) standard
Verilog-AMS Technical Committee - Analog/mixed-signal extensions to Verilog

The following working groups came from OSCI:

AMS- Analog/mixed-signal extensions to SystemC
Configuration, Control and Inspection - Standards for exchange of information between SystemC models and tools
Language - SystemC language standard
Synthesis - Synthesizable subset of SystemC
Transaction Level Modeling (TLM) - OSCI TLM 1.0 and 2.0 modeling standards

Both OSCI and Accellera targeted eventual IEEE standardization. IEEE working groups supported by the Accellera Systems Initiative include IEEE 1076 (VHDL), IEEE 1800 (SystemVerilog), IEEE 1801 (Unified Power Format), and IEEE 1666 (SystemC).

Further information will be available at the Accellera Systems Initiative web site (site temporarily unavailable until Dec. 6).

Richard Goering

Free, On-Demand “Tech on Tour” – Digital, Custom/Analog, and PCB

rgoering — Thu, 01 Dec 2011 14:00:00 GMT

For some time Cadence has offered EDA360 "Technology on Tour" presentations in various cities. Now Cadence is offering on-line Technology on Tour presentations at your desktop, any time, for free. These technical presentations and demos show how to solve common design challenges, and provide the latest information about Cadence custom/analog, digital, and PCB design technologies.

Most of the presentations are in the 30 minute to one hour range, although a few are shorter. Many include both slide presentations and demos. The sessions are available to Cadence Community members (quick, free registration if you're not one yet). You can also sign up for live chat sessions at scheduled times.

To get a feel for these offerings I watched a presentation on trends in 28nm design by Wei Lii Tan, senior product marketing manager at Cadence. In this informative, 40-minute presentation, Tan identified three 28nm challenges - design size and complexity, timing variability, and manufacturability. He then showed how the Cadence 28nm unified digital flow addresses these issues. Areas of focus included multi-mode/multi-corner, on-chip variation (OCV), low power, physically aware synthesis, hierarchical design closure, and the new FlexModels technology.

The presentation also included several demonstrations. One showed how a new methodology, post-assembly closure, can close timing at the top level without requiring a lot of iterations between the block level and top level. Another illustrated lithography hot-spot prevention and in-design DFM signoff. A third showed how NanoRoute inserts double-cut vias and spreads wires to boost manufacturability.

Here's a listing of the currently available Technology on Tour On Demand sessions.

Custom/Analog Track

Virtuoso 6.1.5 - Front-End Design Steve Lewis, Product Marketing Director

Highlights of new front-end design tools and features (including a new waveform viewer, Virtuoso Schematic Editor, and Virtuoso Analog Design Environment), and how to identify and analyze parasitic effects early.

Virtuoso Multi-Mode Simulation John Pierce, Product Marketing Director

Updates on the latest simulation capabilities including Virtuoso Accelerated Parallel Simulator distributed multi-core simulation mode for peak performance; a high-performance EMIR flow; Virtuoso Accelerated Parallel Simulator RF analyses; and an enhanced reliability analysis flow.

Virtuoso 6.1.5 - Top-Down AMS Design and Verification John Pierce, Product Marketing Director

Highlights of the latest in advanced mixed-signal verification methodology, checkboard analysis, assertions, and how to travel seamlessly among all levels of abstraction of the design.

Virtuoso 6.1.5 - Back-End Design Steve Lewis, Product Marketing Director

Highlights of the latest in constraint-driven design; Virtuoso Layout Suite; links between parasitic-aware design, rapid analog prototyping, and QRC Extraction; and top-down physical design: floorplanning, pin optimization, and chip assembly routing with Virtuoso Spaced-Based Router.

Virtuoso 6.1.5 - MS Design Implementation Michael Linnik, Sr. Sales Technical Leader

Highlights of the latest mixed-signal implementation challenges and solutions that link Virtuoso and Encounter technologies on the OpenAccess database, including analog/digital data interoperability, common mixed-signal design intent, advances in design abstraction, concurrent floorplanning, mixed-signal routing, and late-stage ECOs.

What's New in Signoff Hitendra Divecha, Sr. Product Marketing Manager

Highlights of standalone and qualified in-design signoff engines for parasitic extraction, physical verification, power-rail integrity analysis, litho hotspot analysis, and chemical-mechanical polishing (CMP) analysis.

Digital Track

Trends in Digital Design (28nm Design) Wei Lii Tan, Sr. Product Marketing Manager

Find out what's needed to be ready for 28nm design - process variation, power-performance-area optimization, DFM considerations, and more.

Trends in Digital Design (ECOs) Kenneth Chang, Sr. Product Marketing Manager

Find out what's needed to handle the increasing complexity of ECOs and their impact on schedule. Leverage a front-to-back automated ECO flow that can help you achieve a 3x gain in productivity and a much faster path to design tapeout.

Digital Design Technologies David Stratman, Sr. Product Marketing Manager

Highlights of new physically-aware technologies including physical synthesis and test; new constraint design capabilities including clock-domain-crossing (CDC) checks, low-power ATPG, and precision diagnostics flows; and low-power interoperability support.

Digital Implementation Technologies Wei Lii Tan, Sr. Product Marketing Manager

Highlights of new digital implementation technologies including design exploration with automatic macro-placement and flexible models; post-assembly closure for hierarchical implementation; new and improved optimization and clock-tree synthesis (CTS) during block implementation; and the latest mixed-signal capabilities across digital and custom design environments.

Digital Signoff Technologies Hitendra Divecha, Sr. Product Marketing Manager

Highlights of standalone and qualified in-design signoff engines for parasitic extraction, physical verification, timing, power-rail integrity analysis, litho

PCB Design Track

Allegro 16.5 - PCB Design Authoring (including FPGA-PCB co-design) Umar Shah, Sr. Sales Technical Leader

Technical presentation highlighting the newest capabilities for front-end PCB design, and a demo of FPGA-PCB co-design using Allegro FPGA System Planner.

Allegro 16.5 - Concurrent Team Design Authoring Umar Shah and Shawn Nikoukary, Sr. Sales Technical Leaders

Technical presentation and demo illustrating the concept of concurrent team design authoring; how it can encourage design reuse and make your design creation cycle shorter and more predictable.

Allegro 16.5 - Power Delivery Network Shawn Nikoukary, Sr. Sales Technical Leader

Technical presentation and demo on power delivery network analysis and how an integrated design and analysis solution, with no translation required, helps you converge on a working solution efficiently.

Allegro 16.5 - Design Planning Umar Shah, Sr. Sales Technical Leader

Technical presentation and demo on design planning to shorten the time to plan your interconnects and reduce the layer counts.

Allegro 16.5 - Signal Integrity Shawn Nikoukary, Sr. Sales Technical Leader

Technical presentation and demo on what's new in signal integrity. See advances in multi-gigabit analysis as well as DDR3 timing closure through integration with our technology partner's tool, TimingDesigner.

Happy viewing!

Richard Goering

ARM TechCon Paper: Early Architectural Planning With a Digital Implementation Flow

rgoering — Wed, 30 Nov 2011 14:00:00 GMT

You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that Cisco is using to do pre-RTL architectural analysis with Encounter.

The paper was titled "Early Architectural Planning for Increased Productivity, Predictability and Profitability," and was presented by Abha Maheshwari, product manager at Cadence, and Krishna Kumar, senior hardware engineer at Cisco. Proceedings are available to conference attendees at the ARM TechCon web site.

In brief, the flow captures design and technology information in a text file, uses a Tcl script to create a netlist, and then uses the automated floorplan synthesis capability in Encounter to generate an early floorplan. Cisco engineers can then obtain early die size and cost estimates, try different architectural alternatives, and develop a preliminary floorplan that can be provided to an ASIC vendor.

"Using our place and route solution and some scripts, we've been able to come up with a complete flow to do architectural analysis very early in the design stage before you even have any RTL ready," Maheshwari said. She summarized the advantages of this approach in the following slide:

Kumar then talked about Cisco's motivations for adopting early architectural analysis. He noted that his group targets different market segments with its networking ASICs, and must meet different requirements. Further, at advanced nodes, wire delays are dominating cell delays. "This means your top level implementation is going to be much more critical," he said. "The best way is to start very early in the design cycle, without coding any RTL, and do an analysis of the design and find out where the bottlenecks are."

Automated Assistance

Kumar walked through the architectural analysis flow in detail. It starts with the capture of chip architecture and IP information in a text file. Then, a simple Tcl script creates a netlist from this early architectural information. The script adds dummy cells, dummy flops, dummy or real memory, pipeline stage registers, timing constraints, and clock definitions.

An interactive schematic visualization capability in Encounter lets designers view and check the connectivity between different modules. The Encounter GUI can also help designers analyze the implementation feasibility of dummy memory and IP elements. Additionally, Encounter helps Cisco engineers verify pipeline flip-flop insertion, and set up bus guides and net groups.

The next step is automated floorplan synthesis, which was described by Maheshwari. She showed how this capability can take in seed information (or generate its own), optimize the data path, place modules and hard macros, and "provide a very good starting point floorplan in a short amount of time." Designers can generate multiple floorplans and select the best one to meet their goals.

From Two Months to Two Weeks

During his presentation, Kumar noted that prior to using the early architectural flow, Cisco would sometimes wait 2-3 months for an ASIC vendor to come back with die size and cost information. "Right now we are able to do this in two weeks, because everything is done in house without any RTL," he said. Today, he noted, Cisco and Cadence are working together to develop and strengthen capabilities such as automatic bus guide creation, identification and placement of pipeline flops, and what-if analysis for the top-level pipeline. Present and future Encounter Digital Implementation System users will benefit from this work.

Richard Goering

Other blog posts about ARM TechCon 2011 papers:

ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs

ARM TechCon Paper: Why DRAM Latency is Getting Worse

ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development

Want Better EDA Tool Performance? How Cadence IT Can Help

rgoering — Mon, 28 Nov 2011 14:00:00 GMT

Would you like your EDA tools to run or load faster? Do you want to quickly and securely resolve any tool-related issues you experience with Cadence products? The Cadence IT group has a couple of programs that can help. One is the recent Customer Collaboration Initiative (CCI), which focuses mostly on product issues, and another is the Cadence EDA Infrastructure Acceleration Services, which helps customers improve their underlying CAD infrastructures.

As I noted in a previous blog post, the Cadence IT experts are not content to stay within company walls (figuratively, I mean). In concert with Cadence sales and services organizations, they're actively helping customers get the most out of their EDA compute infrastructures and Cadence tools. They're providing secure ways to debug problems, and they're helping resolve common infrastructure issues with operating systems, storage, and networking.

This is a new direction for the EDA industry and perhaps a new business model. "It's clear that when we get into customer sites that our competitors aren't doing anything like this," said Joe Macaluso, IT senior program manager at Cadence. "They're not deploying any IT resources and they're not helping customers solve any IT related issues."

Secure Debugging

The objective of CCI is to establish a collaborative infrastructure with Cadence customers for faster issue resolution, real-time collaboration, and increased productivity using Cadence tools. Charles Byrd, CCI program lead, noted that the program is used for debugging problems, engineer-to-engineer collaboration, tool introduction, design collaboration, and benchmarking.

There are two main technology offerings within CCI. One is VCAD chambers, which have provided physically secure compute environments at Cadence for many years. Customers can upload their data into a firewall-protected VCAD chamber, put together some test cases, and work with Cadence personnel to debug problems. Another offering, Imera, provides a remote GDB debug capability. Imera supports peer-to-peer collaboration and makes it possible to share a desktop with Cadence personnel, while all customer data remains at the customer site.

With this year's CCI rollout, Byrd said, "we created a duplicatable process that is quite streamlined" and that provides a single point of contact for the customer. Through CCI, Cadence experts can resolve a broad range of issues "without having to put people on flights to look at the data," as Macaluso put it. Sometimes, though, what appears to be a tool issue is really an infrastructure issue. And that's there the EDA Infrastructure Acceleration Services comes in.

Making Tools Run Faster

Macaluso said that there are three major categories of infrastructure problems that make tools load or run slowly, or not perform to expectations. They are:

Operating system issues. Sometimes Linux versions are out of date or are not optimized to run tools efficiently. Also, many companies don't have a repeatable process for imaging hardware. That task may take 60 or 70 steps, and if an engineer has to image 20 machines manually, "you'll probably get 16 different images of the OS," Macaluso said.
Storage. "EDA hammers storage," Macaluso said. "There are a lot of challenges with storage and with accessing volumes of data. Having the right storage setup is key."
Networking. Sometimes routing is incorrect or ports are not set up correctly, or there is a mismatch in data rates between the rack and a device. "Our recommendations are typically in terms of network monitoring and understanding where your congestion points are," Macaluso said.

Beyond these common problems, Macaluso noted, sometimes customers just need a better understanding of how the infrastructure was designed and intended to be used. They may try to use an interactive machine to do a batch job, use non-optimized generic wrappers to load tools, or use a wrapper for an old tool version that has different compute requirements.

Byrd noted that "some customers will launch a Cadence tool and it takes a long time to load. We come in and analyze it, and we chop it to a fraction of the time, basically making sure customers are getting what they paid for and that the software is usable and does its job. The configuration of the environment can have a dramatic impact on how tools perform."

It all makes sense. The people who run IT for the people who develop EDA tools are in an excellent position to help EDA customers get the most for their money.

Richard Goering

ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development

rgoering — Mon, 21 Nov 2011 14:00:00 GMT

You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in a paper presented at the recent ARM TechCon conference by Jason Andrews, senior architect at Cadence.

The paper was titled "Creation and Usage of SystemC Virtual Platforms for Multi-Core System Debugging and Analysis," and was given Oct. 27. Proceedings are available to conference attendees at the ARM TechCon web site. A video of the presentation is available here and is also embedded below.

A virtual platform, Andrews noted, makes it possible to simulate hardware using SystemC, and to then run software on top of that simulated hardware. "It's all simulation," he noted. "Everything you'll hear about today runs on a workstation - no boards, no cables." While simulation has been used for software development for many years, the commercial virtual platform market is relatively new. Two standards that make this possible are SystemC (IEEE 1666), a set of classes on top of C++, and the Open SystemC Initiative (OSCI) transaction-level modeling (TLM 2.0) standard, which permits a high level of modeling abstraction.

As shown in the following diagram of the Cadence System Development Suite, virtual platforms are part of a larger hardware/software development continuum, and are used very early in the design flow:

Multi-core Example

To show how virtual platforms are created and how they work, Andrews used an example of a multi-core design. It includes a dual ARM Cortex-A9 processor with an L2 cache, an ARM Cortex-M3 processor, LPDDR2 controller, SRAM, ROM, UART, and timers, among other components. He then walked through a detailed example showing how a virtual platform was created for this design. Some of the key steps included:

Generating SystemC TLM models for peripherals using an automated model generator
Producing a register description (both individual registers and register banks)
Customizing the generated model, adding the "behavior behind the registers"
Using a memory map for the dual Cortex-A9
Using ARM Fast Models for the processors (don't write SystemC models for these!)

What you end up with is a virtual platform that contains Fast Models for the ARM processors and SystemC models for all the peripherals. The ARM models take binary instructions and run software on a laptop or workstation at a very high rate of speed.

When designers plug everything together, Andrews said, "it never works" the first time. He reviewed a number of common problems that arise with virtual platforms. These include system integration issues such as a program memory that's too small, device driver crashes due to missing hardware, and problems with interrupts. The Direct Memory Interface (DMI), which lets SystemC models read directly into memory, is also a potential source of problems. Andrews also reviewed common problems made during model creation.

Andrews then showed how to set up a secure boot sequence for the Cortex-A9 and Cortex-M3, and reviewed potential problems such as poor synchronization of access to shared RAM and difficulties with the interrupt configuration.

Virtual Platform Debugging

Once the platform Is set up and simulation is running, designers will want to start debugging. "The first thing everybody tries is debugging software," Andrews noted. This can be done with a software debugger that shows what's going on in the various processor cores, displays register values, allows single-stepping, and provides other features one would expect from a software debugger. But just looking at software may not enough. Multi-core systems use frequent interrupts, and problems with interrupts are common.

"Now you're thinking you want something like a logic analyzer, and you want to see all the interrupt lines," Andrews said. "Well, in a virtual platform you can see hardware behavior that is harder to see on your board." This was a common theme in the presentation - that virtual platforms make it possible to observe hardware behavior that would be difficult to see in real hardware.

Andrews talked about the profiling capabilities available with virtual platforms, which can be used both to improve simulation speed and to make the system software and hardware implementation more efficient. While it's not easy to profile using real hardware, he noted, a virtual platform allows non-intrusive profiling without the need to instrument code. (For more information on profiling see Andrews' guest blog on the ARM web site, "Using the ARM Profiler with the Cadence Virtual System Platform.")

"For me, creating this type of virtual platform is fun," Andrews concluded. "You learn a lot and you see how things work." He also noted that a lot of companies are training or looking for "virtual platform engineers" who can create and debug the models. It's a chance to "be the hub for all the engineers working on your project," he said.

Click on the icon below to view the video of the presentation, or click here.

Richard Goering

Other blog posts about ARM TechCon 2011 papers:

ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

ARM TechCon Paper: "Tips and Tricks" for ARM Cortex-A15 Designs

ARM TechCon Paper: Why DRAM Latency is Getting Worse

rgoering — Fri, 18 Nov 2011 00:00:00 GMT

There's a general view that everything gets faster and better as technology advances, but when it comes to external memory latency, that's not the case. In a recent ARM TechCon paper Marc Greenberg, director of product marketing at Cadence, showed why DRAM latency is increasing and discussed ways of improving the situation.

The paper was titled "DDR4, Higher Speeds and Larger SoCs: Why External Memory Latency is Getting Worse, and What to do About it." It was presented before a standing-room-only audience Oct. 25. You can read an article by Marc Greenberg on the same topic in the Nov. 22 ChipEstimate.com newsletter. A video of the presentation is embedded below and you can also click here to view it.

Greenberg started the ARM TechCon presentation by showing a chart, based on publicly available data, that predicts a DDR4 read latency of 22 clock cycles for the highest DDR4 data rate. The chart assumes an average latency of around 13.5 ns and is basically a plot of 13.5 ns against the clock periods of the various DRAM types. "Basically the DRAM cell array hasn't changed in the past 10 years," he explained. "At its core is a 100 MHz to 200 MHz array that has an access time of about 10 to 15 ns."

RL-tRCD (RAS to CAS delay)-tRP (read-to-precharge) of DDR3 DRAM by speed grade, with curve-fit prediction for DDR4.

DRAM is getting faster, Greenberg noted, because successive DRAM technology generations are increasingly parallelizing the array. With DDR3, for example, you can send transactions to 8 arrays in parallel. So even though the DRAM data rate has increased by over 10X in the past ten years, and CPU clock frequency has increased by over 10X, "the latency really hasn't changed," Greenberg said. "In fact, if you measure it in clock cycles it's been getting worse."

How Can We Improve?

In discussing ways to improve the situation, Greenberg pointed to some options that are in many cases impractical. He first warned that while reducing minimum CPU-to-DRAM latency is important, it should not be done at the expense of average latency, or at the expense of DRAM bandwidth. It is possible to make a very low latency DRAM controller that doesn't do any reordering of transactions, but that will come at the expense of DRAM bandwidth.

Video: Why TSMC Cares About System-Level Design

rgoering — Wed, 16 Nov 2011 14:00:00 GMT

Why would TSMC, the world's largest foundry, care enough about electronic system-level (ESL) design to include it in a reference flow? In the short video clip embedded below, Ashok Mehta, senior manager of system verification and software architecture at TSMC, explains why and how his company worked with Cadence to develop the ESL portion of TSMC Reference Flow 12.

Here's a bit of background. In 2010 TSMC announced its Reference Flow 11, which broke new ground by extending TSMC's Open Innovation Platform to system-level design. Cadence worked with TSMC on high-level synthesis and on a "refine and reuse" verification methodology that allowed the reuse of models and testbenches at different levels of abstraction. In Sept. 2010 I blogged about what Cadence and TSMC learned from Reference Flow 11.

In June 2011 TSMC rolled out Reference Flow 12, which also included ESL in addition to other technology areas. While Reference Flow 11 was aimed at the block level, Reference Flow 12 extends to the virtual platform level. Using the Cadence Virtual System Platform, it shows how to build a virtual platform, develop a software application, boot Linux, and estimate power. The reference flow includes a migration path that goes from TLM all the way to RTL.

Interviewed in an Industry Insights blog post about the ESL portion of Reference Flow 12, Mehta noted that one of TSMC's motivations is to enable customers to get early power estimations. "Power is the center pole, and everything else surrounds it," he said.

In the video clip, Mehta notes that "the current RTL centric methodology is clearly not working. We must raise the abstraction level from the RTL to the system level to address increasing complexity, and also reduce the time to market." He discusses the reference flow and the tight collaboration that made it possible, and explains TSMC's motivations.

If video icon does not open, click here to access the video.

I think the ESL portion of Reference Flow 12 shows that TSMC is an exceptionally forward-looking foundry. But then, you don't remain an industry leader without leading the way when paradigms shift.

Richard Goering

Archived Webinar: Which Verification Coverage Metrics to Use When

rgoering — Mon, 14 Nov 2011 16:20:00 GMT

What metrics matter most at different stages of the verification process? How can metrics be leveraged to reduce the risk of failures in your IC designs? These questions were answered in a recently archived Cadence webinar that offers a comprehensive primer on the use of code coverage, functional coverage, and assertions in functional verification.

Titled "What Metrics Matter - a User's Perspective on Coverage," the webinar was presented by John Brennan, product marketing director at Cadence, and John Nehls, solutions architect at Cadence. The webinar is available for viewing here. Some highlights from the webinar follow.

At the start of the webinar, Nehls noted that the cost of fixing a bug increases exponentially the later the bug is found. "Putting additional effort into the verification process up front is what customers are trying to achieve, and the way it's done is through metrics," he said. "Knowing what metrics matter at certain points of the design process is really critical." Highly productive teams, Nehls said, use all three kinds of metrics - code, functional, and assertions - in a complementary way.

"Are We Done Yet?"

The question verification managers always ask, Nehls said, is "are we done yet." Often this is answered based on emotions or intuition. Perhaps the team is out of money or is exhausted, the competitor's product is already shipping, the software people seem happy, the boss says "ship it," or there are no bugs for two weeks. "What we're suggesting is a more rigorous criteria with concrete goals established," Nehls said. "We are moving from a subjective view of the verification process to a quantitative view."

There is a name for this approach - metric-driven verification (MDV). Nehls defined it as "the notion of applying rigorous criteria to metrics from multiple sources and managing them to completion." A critical aspect of MDV is starting with a verification plan that considers the goals of the verification process, the key features and functions that need to be verified, and the approaches that are needed to verify a particular function. Then teams can execute the verification, collect coverage metrics, and bring the results back into the verification plan in a single view. Teams can apply different metrics for different parts of the verification effort, and can use both simulation and formal analysis.

Nehls spoke about the different types of metrics and where they are best applied. Code coverage, for example, is a measure of how well the RTL code is exercised, and isn't very useful until there is a robust testbench and thorough functional coverage is already underway. This occurs during the IP verification phase. Later on, in SoC level verification, a type of code coverage called "toggle coverage" (which tracks activity on signals) is very useful for verifying integration and connectivity.

Assertions can be used much earlier, starting with the block-level verification done by designers. The same assertions can then be reused by verification engineers during IP verification and SoC level verification. Assertions can be used in both simulation and pure formal verification. Formal, assertion-based verification is very useful for certain types of blocks, as Nehls described.

Functional coverage can be used by designers for block-level testing, but these "smoke" tests are not generally reusable. The "sweet spot" for functional coverage is during IP verification with constrained-random simulation. At the SoC level, functional coverage can be used to find integration-level bugs as well, but here the testing is more directed and scenario-based.

A Closer Look

Nehls went on to provide a lot of detail about code coverage, assertion coverage, and functional coverage. He identified four types of code coverage - block, toggle, expression, and finite state machine - and explained their description, advantages, disadvantages, and use cases. Overall, code coverage is complementary to functional coverage and is "necessary but not sufficient" by itself. It does not ensure that functionality is completely covered and cannot detect missing features.

Assertions, Nehls noted, can be used in a number of ways "that do not require you to be a formal verification expert." One way assertions can be used is to find unreachable code, which can save a great deal of wasted effort. Nehls explained how assertions can be used in both formal analysis and simulation, and how these two verification modes can be used together.

Nehls showed how functional coverage verifies the functionality of the design, and how it's implemented with coverage constructs in testbench code, with examples in both SystemVerilog and e. He also showed how to build a meaningful coverage model, which is essential for success with functional coverage. Like code coverage, functional coverage has some limitations. There is no automatic way to check that the coverage model is correct, and there is still a possibility of not exercising some parts of the HDL code.

Bringing it All Together

Finally, Nehls showed how an executable verification plan can bring all the metrics together into a single view. One tool that provides this capability is the Incisive Enterprise Manager. Said Brennan: "Metrics do matter, and being able to roll them up in a reasonable way, where you can see all aspects of all metrics in one spot at one time, is really critical for the overall verification process. It really provides a quantifiable and undisputable mechanism or knowing when you are done."

Want to learn more? View the webinar by clicking here.

Richard Goering

EDA “Nobel Prize” Goes to Algorithmic Pioneer

rgoering — Fri, 11 Nov 2011 01:23:00 GMT

The annual Phil Kaufman award, which honors individuals who have made a significant impact on electronic design automation, is the EDA industry's equivalent of the Nobel Prize. This year's award was presented Nov. 8 at a dinner event in San Jose, California, sponsored by the EDA Consortium and the IEEE Council on EDA (CEDA). The recipient was Dr. C.L. David Liu (right), a longtime professor in both the U.S. and Taiwan and one of the academic founders of EDA.

In my many years of EDA reporting I never talked to Dr. Liu, but if it were not for his industry contributions, I wouldn't have had as much to write about. Several times at the dinner, Dr. Liu was hailed as the man who "led the transformation from ad-hoc EDA to algorithmic EDA." He developed many of the mathematical foundations of tools like floorplanning, routing, placement, and synthesis. He also contributed heavily to embedded software development and wrote several key textbooks on computer science.

Here are a few quick facts about Dr. Liu's career (and so-called "retirement"):

Came to the U.S. in 1958 as an undergrad at MIT and stayed there until 1972.
Professor at the University of Illinois, Champaign-Urbana, from 1973-1998.
Returned to Taiwan in 1998 to become president of National Tsing Hua University until 2002.
On the board of a number of companies, including United Microelectronics Corp. (UMC) and MediaTek.
Hosts weekly radio talk show in Taiwan on subjects including technology, natural science, social science, and literature. Published several essay collections based on presentations in the show and won a 2011 book award in popular science.

I learned a lot more in a speech by Jason Cong, professor at the University of California at Los Angeles, who admitted he was a bit nervous speaking in front of (and about) his former PhD advisor, Dr. Liu. Speaking of the award nomination process, he asked, "how many EDA pioneers are on the board of a major semiconductor foundry, several major fabless semiconductor companies, president of a prominent international research university, PhD advisor to a Turing award winner, and has his own radio talk show? We believe the answer is exactly one, and that's Dave."

Cong outlined Dr. Liu's career in more detail, including his first Design Automation Conference (DAC) paper in 1982, and his receipt of a DAC Best Paper award in 1986 for some foundational work in floorplanning algorithms. In addition to floorplanning, Cong said, Dr. Liu's contributions are reflected in over-the-cell channel routing, performance-driven placement, scheduling, and optimal clock period FPGA mapping. "The breadth of Dave's work covers the entire implementation flow, from routing to placement to logic synthesis and behavioral synthesis," Cong said.

Dr. Liu's work isn't just about EDA. A 1973 paper on Rate Monotonic Scheduling (RMS) describes algorithms widely used in real-time embedded systems today, and the paper has received over 7,000 citations (in academia, 100 citations is considered "good"). Dr. Liu also wrote or co-authored several computer science textbooks. If you've studied computer science, you may have used one of these:

Introduction to Combinatorial Mathematics, 1968
Linear Systems Analysis, 1975
Elements of Discrete Mathematics, 1977
Pascal, 1984

Cong said that Dr. Liu is humorous, humble and a great speaker, and Dr. Liu exhibited all these qualities in a short acceptance speech. "Thank you for reminding me how grateful I should be," he said. "When I look at the impact of electronic design automation on this multi-billion dollar semiconductor industry, when I look at EDA by itself, when I look at all the intellectual giants, the industrial leaders, and the young, energetic minds in our profession, I am humbled and so fortunate that I could be a small player in this great landscape."

It seems the rest of us are fortunate for Dr. Liu's contributions.

Richard Goering

IEEE Revises SystemC for 2011 – What’s In It For Users

rgoering — Thu, 10 Nov 2011 15:00:00 GMT

More than any other language standard, SystemC has made system-level design possible. It is the lifeblood of high-level synthesis, virtual prototyping, and transaction-level verification. Thus, the first IEEE revision of the standard in six years -- announced today (Nov. 10, 2011) as IEEE 1666-2011 -- is a milestone event for all who are using SystemC or may be doing so in the future.

The IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666 "Standard SystemC Language Reference Manual," and it is expected to be available early next year. Compared to the original IEEE 1666-2005 standard, the new standard has a number of clarifications and bug fixes, has been expanded to include the transaction-level modeling (TLM) interfaces developed by the Open SystemC Initiative (OSCI), and has added some important new language features such as the process control constructs noted below.

With IEEE 1666-2001, said Stan Krolikoski (right), chair of the IEEE 1666 Working Group and group director of standards at Cadence, "there is no question [SystemC] is a real standard." To gain even more international recognition, he noted, the SystemC standardization effort will now move on to the International Electrotechnical Commission (IEC).

Additions to the 2011 Standard

The OSCI TLM interfaces help enable interoperability and reuse for SystemC models. TLM 1.0 defines a standard set of APIs for transaction-level communications, but does not define the content of the communications. TLM 2.0 defines the content of transactions with a "generic payload" and also identifies two levels of transaction-level modeling - Loosely Timed (LT) and Approximately Timed (AT). The TLM nomenclature may be a bit confusing in that TLM 1.0 is not a direct subset of TLM 2.0.

In addition to adding the TLM interfaces to the LRM, the IEEE 1666 Working Group has clarified their descriptions and fixed bugs, Krolikoski noted. Now, he said, "it's in one spot, it's cleaned up and it is the official standard." While widely used today, OSCI TLM 1.0 and TLM 2.0 have not been IEEE standards until now.

There are other new features in the 2011 standard as well. One is process control constructs, which I blogged about earlier this year. In short, processes are basic behavioral entities in SystemC, but the 2005 standard lacked a direct API for controlling one process from another. The new process control constructs make it possible for one process to suspend-resume, disable-enable, or kill/reset another. This is useful for developing testbenches, modeling asynchronous resets or triggers, or simulating events such as a sudden power loss to a computer.

Process control constructs are based on a specification written by Cadence and submitted to OSCI several years ago. They are supported in the Cadence Incisive Enterprise Simulator. A 2009 Cadence paper describes further details about their use.

Cleaning and Expanding

Other new features in IEEE 1666-2011 include the following:

Event list objects
Hierarchically named events
Multiple writer policy for sc_signals
Asynchronous update requests for primitive channels
Binding operators for sc_port and sc_export are now virtual
Certain fixed-point constructors have been made explicit

Beyond these new features, Krolikoski noted, were a number of small clarifications and bug fixes. "SystemC really took hold after its standardization in 2005, and there were lots of areas where there were questions, and in some cases bugs. We cleaned that up for 2011." Indeed, a lot of people read that 2005 standard. Krolikoski noted that over 50,000 copies of the 2005 LRM have been downloaded, thanks in part to a deal in which OSCI paid the IEEE so the LRMs could be downloaded for free.

IEEE 1666 is a corporate standard (one company, one vote). Members of the IEEE 1666 Working Group include Accellera, Cadence, Freescale, Intel, JEITA, Mentor Graphics, NXP, OSCI, STMicroelectronics, STARC, Synopsys, and Texas Instruments. The 2011 standard was a true international effort, Krolikoski said, and was almost all conducted by email, making it a true Internet-driven standard.

Congratulations to all whose hard work is reflected in the new 2011 SystemC standard!

Richard Goering

ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

rgoering — Wed, 09 Nov 2011 14:00:00 GMT

The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's not just theoretical - the paper also showed how the methodology was applied to a groundbreaking HD digital camera system-on-chip (SoC) developed by semiconductor startup Ambarella.

The paper is titled "Creating an Effective 32/28nm ARM SoC Design Methodology," and is authored by Moo Young Park, director at Samsung; Wei Lii Tan, senior product marketing manager at Cadence; and Ankur Gupta, director of product engineering at Cadence. Gupta presented the paper at ARM TechCon Oct. 25. (Note: Proceedings are available to conference attendees at the ARM TechCon web site).

First, a few words about the Ambarella A7L SoC, a chip that promises to usher in a new generation of HD video enabled digital cameras. Ambarella announced availability of the chip in September 2011, and Cadence and Samsung followed up Oct. 25 with an announcement of their collaboration on the chip. The A7L was designed using Samsung's 32nm low-power, high-k metal gate (HKMG) technology and ARM 32nm libraries along with the Cadence Encounter Digital Implementation System and Encounter RTL Compiler. The chip contains an ARM 1136, several million logic gates, and a number of high-speed mixed-signal blocks.

Working side-by-side, engineers from Cadence, Samsung and Ambarella were able to achieve a 95% power savings during power shutoff mode and a 60% average power savings over operation and sleep modes. The end result: an SoC that supports full 1080p HD H.264 video at 60 frames per second for fluid motion even during fast moving sports scenes, and can capture up to thirty 16-megapixel still images per second. For more details on the chip see Steve Leibson's recent EDA360 Insider posts.

A 32/28nm Methodology

Gupta began his presentation by noting 32/28nm challenges in several key areas. One is the complexity brought about by larger gate counts. Another is leakage power, although this can be reduced with HKMG technology. Timing variability becomes a big concern because of high interconnect and via resistance and variation, as well as the impact of stress on timing. To model variability, it is necessary to model not only individual transistor delays but to consider the placement of transistors near one another. Finally, design for manufacturability (DFM) becomes more challenging, and designers must cope with over 200 new routing rules.

The slide below shows a 32/28nm design methodology that can resolve these challenges. Many of the capabilities shown here were used to design the Ambarella chip. Some key aspects of this flow include physically-aware synthesis, clock concurrent optimization, design rule checking (DRC) and DFM aware routing, fast DFM analysis, and an ability to prune the number of corners that need to be analyzed during the design.

Cadence, Samsung, and Ambarella actually completed two tapeouts - the T32 test chip came first, followed by the A7L Media Processor. Gupta noted that the A7L represented several "firsts," including the first 32nm external customer design project done by Samsung and the first dual row I/O architecture applied to a 32nm process. To reduce chip size, Samsung developed a smaller pitch I/O power cell. To reduce leakage, a dual-Vt layout flow was used.

Synthesis, Power, Clocking, and More

Gupta then took a more detailed look at the methodology that was used to build the Ambarella chip. Key points included the following:

Physical synthesis is very important at 32/28nm. Wiring needs to be aware of congestion and routing layers, and wire-load models don't support that.
Power shutoff is a powerful technique for minimizing leakage but is complicated to implement. It requires additional logic such as isolation cells and always-on buffers. It's important to capture power intent. The Ambarella project used the Common Power Format (CPF) to do so.
Clock tree synthesis should not be rigidly based on "zero skew." The T32 and A7L projects used a more flexible concept called "useful skew." Better yet is clock concurrent optimization, which was not available in time for these projects but is offered by Cadence today. This approach combines clock tree synthesis with physical optimization and provides significant power, performance and area benefits. A new Chip Design Magazine article has detailed information.
Corners need to be "pruned" during design to avoid excessive analysis times. The T32 test chip had four multi-mode/multi-corner "views" while the A7L SoC had six. But there were around 20 signoff views. Timing violations at final signoff were fixed using an ECO script.
Using higher routing layers at 32/28nm can help with timing closure. Higher layers have lower resistance and lower RC delay constants. In the T32 and A7L, higher routing layers were utilized to close timing for critical paths.
Lithography analysis is needed at 32/28nm because even DRC-clean locations may not print correctly. Cadence worked with Samsung to identify lithography hot spots.
Finally, advanced node support must extend to the custom/analog environment. "For advanced nodes, custom and library design is where the challenges start," Gupta said.

The result speaks for itself. The A7L, which is available today, met performance targets and achieved first-time success using Cadence digital implementation tools, the Samsung 32nm LP HKMG process, and ARM libraries and power management kit. It also achieved a significant power savings. Where Ambarella has gone before, others will surely follow.

Richard Goering

Archived Webinar: Bringing SystemC and C/C++ Models into UVM

rgoering — Mon, 07 Nov 2011 14:00:00 GMT

If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence developed for the Universal Verification Methodology (UVM), available as an open-source contribution at http://www.uvmworld.org/.

The webinar is titled "Oceans of Expertise Connecting the UVM to Sea (C/C++/SC)." Presenters are Adam Sherer, product marketing director at Cadence, and Phu Huynh, verification architect at Cadence. Sherer is also secretary of the Accellera committee that's working on UVM.

First, a bit of background. UVM 1.0 and 1.1, as standardized by Accellera, describe a verification methodology for SystemVerilog. The Cadence UVM-ML (multi-language) donation extends UVM to the e language and SystemC (although this webinar was focused on SystemC). Sherer noted in the webinar that Accellera is not expected to consider a multi-language version of UVM until after the release of UVM 1.2 next year. So for now, what was discussed in the webinar is freely available but is not yet an Accellera standard.

Why Multiple Languages?

A system-on-chip (SoC) verification project today can be like the proverbial Tower of Babel. As shown at right, Verification IP (VIP) and universal verification components (UVCs) may exist in different languages, including SystemVerilog, e, SystemC, or C/C++. If you want to put all this together into a UVM style testbench, you need something that makes it possible to coordinate and synchronize those verification components.

Sherer took a quick poll at the start of the webinar and found that most attendees use the SystemVerilog Direct Programming Interface (DPI) to connect SystemC or C/C++ models to UVM. "DPI is good, but one of the problems is that you don't have any standard API to connect the SystemC or C++ components to UVM," Huynh said. "That is what we are trying to address with the multi-language UVM solution."

Huynh noted that there are some issues to be taken care of when integrating components from different language domains. These include synchronizing the execution and phases of components, communicating between the components, and providing some unified common utilities. To allow synchronization and communication, the UVM-ML capability uses the Open SystemC Initiative (OSCI) transaction-level modeling (TLM) standard. (Note: examples in this webinar were given in TLM 1.0, but Cadence is also developing a TLM 2.0 capability for UVM-ML).

Key TLM Terminology

In the webinar, Huynh reviewed some of the basic concepts behind the TLM interface. Important terms include "port" and "export" and "initiator" and "target." For example, when a consumer pulls items from a producer using a TLM "get" function, the consumer is the initiator (see below). Conversely, when a producer pushes items to a consumer using a "put" function, the producer is the initiator. The "port" is the component that initiates the TLM operation, and the "export" is the component that implements the TLM operation. (A questioner noted, and Huynh agreed, that this SystemC terminology is backwards from what some people would expect).

To make a connection, Huynh explained, the user "wraps" the C language model with a SystemC wrapper that provides the required TLM port and export. The synchronization of phases (such as end_of_elaboration and end_of_simulation) is handled automatically by the Cadence UVM-ML extensions. As Huynh noted several times, there are just three basic steps to connecting SystemC components into UVM:

Make sure the transaction exists on both sides (ensure you can transfer transactions across language boundaries, with the same class name and order and type of class variables)
Register the TLM port/export of the components using the UVM-ML library registration method
Make the connection via TLM port and export, using methodology defined in UVM-ML

Huynh showed an example in which a SystemC reference model for a packet router was brought into a UVM verification environment and integrated into a UVM testbench. He also showed multi-language debugging using the Cadence Incisive SimVision interface. You can see this example for yourself on the UVM World site.

In summary, I think the webinar did represent "oceans of expertise" that you can tap into in order to develop a multi-language capability with UVM. But Cadence has already handled a lot of the depth with its UVM-ML contribution. To access the archived webinar, click here.

Richard Goering

ARM TechCon Highlights Roundup – Blogs, Videos, and More

rgoering — Thu, 03 Nov 2011 17:00:00 GMT

The recent ARM TechCon conference was a great success, and so much happened in 3 days there that it's very difficult to keep track of it all. Here's a "coverage roundup" that includes some pointers to blogs, articles, and videos that might help fill in anything you missed - or shed more light on something you saw or heard.

ARM TechCon was held October 25-27 in Santa Clara, California. As I noted in a "preview" blog post in September, it was really two conferences in one - a Chip Design Conference Oct. 25, and a Software & Systems Design Conference Oct. 26-27. Cadence was the official signature sponsor this year and had a number of activities and papers, particularly during the Chip Design Conference.

ARM TechCon - The Week Before

To tell the full story of ARM TechCon 2011, we need to go back in time a week and note two significant developments. One occurred Oct. 18, when ARM and Cadence announced the industry's first 20nm tapeout of the ARM Cortex-A15 processor. That announcement also brought news that ARM and Cadence have worked together to optimize a tool flow for advanced ARM processors. More information about those optimizations is included in the following Industry Insights blog post:

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

The other significant development was the Oct. 19 launch of the ARM Cortex-A7, "the most energy-efficient application class processor ARM has ever developed," according to the press release. There was much discussion at ARM TechCon about this new processor, and the "Big.LITTLE" architecture that allows it to be paired with the ARM Cortex-A15. You can read more about it in Steve Leibson's EDA360 Insider blog post:

ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What's it all mean?

Chip Design Conference

The Chip Design Conference Oct. 25 featured three keynote speeches, including an industry address by Chi-Ping Hsu, senior vice president of R&D at Cadence; paper sessions, including 5 from Cadence; and a "fireside chat" with Cadence CEO Lip-Bu Tan. All events were well attended and some of the paper sessions were standing-room-only events.

The following blog post by Andrew Frame of ARM gives a good general overview with some embedded videos, including a video with Pankaj Mayor, acting head of marketing at Cadence, who provides an update on recent collaborations between Cadence and ARM.

ARM Partner Collaboration in Full Force at Chip Design Day, ARM TechCon 2011

Chi-Ping Hsu Industry Address

In his industry address, Chi-Ping Hsu (right) tackled some of the toughest issues in EDA, including 20nm challenges such as double patterning, and showed how "vertical" collaboration is needed across the semiconductor supply chain. One example of such collaboration was announced that day -- a 32nm ARM-based SoC designed at Ambarella in cooperation with Samsung and Cadence. The following Industry Insights blog post has details about the address:

ARM TechCon Address: High Stakes at Low Process Nodes

Following the industry address, John Donovan of Low-Power Design did two video interviews with Hsu - one focusing on collaboration, the other on low power - as well as an ARM TechCon video interview with Pankaj Mayor. You will find them here.

Paper: Tips and Tricks for Cortex-A15 Designs

Among the many papers given at the Chip Design Conference was a "tips and tricks" paper that showed how Cadence and Texas Instruments successfully pioneered one of the first ARM Cortex-A15 designs. You can read more here:

ARM TechCon Paper: "Tips and Tricks" for Cortex-A15 Designs

Fireside Chat with Lip-Bu Tan

At the "fireside chat," Simon Segars (left in photo below), executive vice-president and general manager of ARM, discussed a number of interesting issues with Lip-Bu Tan. The conversation included vertical collaboration, the prospects for venture funding for semiconductor startups, cloud computing for EDA, making engineering exciting for students, and a recommendation to see the new movie "Moneyball." You can read some highlights in this Industry Insights blog post:

ARM TechCon: Q&A With Lip-Bu Tan, Cadence CEO

This event was also covered by EE Times:

Cadence CEO laments loss of VC in semis

Advice for Designing with ARM Cores

Meanwhile, Steve Leibson had some interesting discussions with ARM executives and wrote a couple of blog posts that will be helpful to anyone designing with ARM processors:

Some critical considerations for SoC and Silicon Realization teams thinking about using ARM Cortex-A7 or ARM Cortex-A8 processor cores

How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011

Software & Systems Design Conference

Zinq-7000 Virtual Platform

Oct. 26 brought news that Xilinx and Cadence have teamed up to develop an "extensible" virtual platform for the Xilinx Zynq-700 Extensible Processing Platform, which includes an ARM Cortex-A9 processor and a 28nm FPGA fabric. The virtual platform will be based on the Cadence Virtual System Platform. Further information is in the following blog posts:

System Design & Verification: Welcome to the Zynq-7000 Virtual Platform

Industry Insights: Virtual Platform for Xilinx Zynq - Why "Extensible" Matters

EDA360 Insider: Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible

64-bit ARMv8 Architecture

The big news Oct. 27 was ARM's announcement of a 64-bit processor architecture called ARMv8. This was revealed in a keynote speech by ARM CTO Mike Muller. Steve Leibson penned these blog posts :

ARM unveils 64-bit v8 architecture at ARM TechCon 2011

AppliedMicro demos FPGA emulation of multicore server chip based on new 64-bit ARMv8 architecture

An ARMv8 technology review by Richard Grisenthwaite, lead architect and fellow at ARM, is available here:

http://www.arm.com/files/downloads/ARMv8_Architecture.pdf

Finally, these blog posts from Lori Kate Smith at ARM provide general overviews of Day 2 and Day 3 at ARM TechCon:

(Day 2) Breadth of ARM Ecosystem Demonstrated at Software and Systems Design Day

(Day 3) ARM TechCon: ARM CTO Announces ARMv8 Architecture, UN, Rubik's Cube & Growth

Parting Shot: "The Week the World Changed"

That's the title of an Industry Note that analyst Gary Smith wrote about ARM TechCon. He admits he's exaggerating, but he views the conference and the ARMv8 announcement as an indication that mainstream computing has "changed significantly."

Want a Replay? EE Times Virtual ARM Conference

Selected portions of ARM TechCon will be repeated at an EE Times "virtual event" Nov. 16 and 17. For information and registration, click here.

Richard Goering

Chi-Ping Hsu photo by Joe Hupcey III

ARM TechCon Paper: “Tips and Tricks” for Cortex-A15 Designs

rgoering — Wed, 02 Nov 2011 13:00:00 GMT

The Cortex-A15 MPCore, ARM's most advanced processor, requires an optimized tool flow and design methodology to meet power, performance and area goals. A paper at the recent ARM TechCon conference showed how Texas Instruments, in collaboration with Cadence and ARM, successfully pioneered one of the earliest Cortex-A15 based designs for the upcoming OMAP 5 platform for mobile devices.

The paper is titled "Flow and Tools, Tips and Tricks: Implementing Successful Cortex-A15 Based Designs." Presenters were Bhasi Kaithamana, implementation manager for ARM processors at TI, and Paddy Mamtora, product engineering director at Cadence. Some of the key takeaways include:

The importance of deep and early collaboration between TI, ARM and Cadence
The advantages of a hierarchical design approach
Reference flows are a good start, but need customization for unique design requirements
Optimal clock distribution requires a non-traditional approach
The connection between synthesis and placement is crucial for this type of design

If you missed the ARM TechCon paper presentation -- or couldn't find a seat at this well-attended presentation -- the paper will be repeated at the EE Times ARM TechCon Virtual Event November 16 at 12:45 pm Pacific time.

A Next-Generation Platform

Kaithamana started the presentation with a quick look at the OMAP 5 platform, which features TI's 28nm low-power process technology, TI SmartReflex power management, and symmetric multi-processing with two ARM Cortex-A15 processors targeting 2GHz plus. The platform also includes two ARM Cortex-A4 processors for low-power offload, and dedicated engines for video, imaging, DSP, 2D and 3D graphics, display, and security. Early samples are expected at the end of this year.

Kaithamana noted that TI has been collaborating with ARM for a long time, going back to the Cortex-A8 device. Mamtora then stepped in and talked about the TI collaboration with Cadence. He spoke of a "very tight collaboration and communication" starting in the summer of 2010, with dedicated on-site Cadence engineers, numerous face-to-face meetings and brainstorming sessions, and a lot of work to understand tool settings and improve flows to meet power, performance and area objectives.

One early decision, Kaithamana said, was to follow a hierarchical design methodology at the CPU level. "It's more efficient to break the design into smaller blocks, and get teams working in parallel," he noted. "You can get the design done more efficiently and get a faster turnaround time." This approach also makes it a lot easier to implement ECOs, he noted.

Mamtora noted that the Cadence unified digital flow supported this hierarchical approach, and he showed a diagram depicting the Cadence tools (in red, below) that were used in this Cortex-A15 based design project. He noted that a tight link between synthesis and placement was crucial for meeting power, performance and area targets. Thus, Cadence developed a common optimization engine to speed timing closure. As a result, what comes out of synthesis is a legal placement.

Kaithamana noted that the TI design flow was customized in order to better meet power, performance and area targets. Examples include a customized "don't use" list for better cell selection, defined cost groups for mapping and incremental optimization, and total negative slack (TNS) optimization for both logical and physical synthesis, which provided more efficient performance and power.

"You can take a reference flow as a starting point but you need to go beyond it to get a more optimized design," he said. Mamtora noted that a Cadence-based reference flow is available for the Cortex-A15, but added that "you need to customize" a reference flow and that customization becomes a source of differentiation.

Rethinking Clocking

Noting that "we don't believe in traditional CTS [clock tree synthesis]," Kaithamana described TI's approach to clocking. In this scheme, clock distribution is done with a clock mesh and a "very shallow" CTS. The mesh performs architectural clock gating, and gives engineers tighter control over insertion delays, skew and latency. Functional clock gating occurs at a lower level. "If we don't do anything pre-CTS the insertion delays are huge and there's a penalty with OCV [on-chip variation]," Kaithamana said.

The clock network was built using a Tcl script developed by TI and Cadence. Since that time Cadence acquired Azuro, and now offers a clock concurrent optimization (ccopt) capability for the Encounter Digital Implementation system (see my previous posting for background). This is a new technology that combines CTS and physical optimization into a single step. Kaithamana said that TI will "transition to ccopt."

Kaithamana cited "lessons learned" during the OMAP 5 project, such as the need to use physical layout estimation (PLE) models for certain blocks, limit usage of high-performance flip-flops during synthesis, and plan power switch topology during placement capture.

He concluded with two main points. One is that each project has different requirements, and needs a customizable implementation flow. Another is the need for very tight collaboration between the design team, IP providers, infrastructure teams, and EDA vendors. Indeed, this ARM TechCon paper is an example of what tight collaboration can achieve.

Richard Goering

Related blog post

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

Webinar: How to Stop “Insidious” Bugs at the HW/SW Interface

rgoering — Mon, 31 Oct 2011 13:00:00 GMT

Meet Sid, the "insidious" hardware/software interface bug. He was the star, so to speak, of a recent Duolog Technologies-Cadence webinar now archived at the Duolog web site. The webinar shows how hardware/software interface bugs arise, how they can be uncovered with help from the Universal Verification Methodology (UVM) register package, and how an automated register management tool can make life even more difficult for Sid and his kind.

The webinar is titled "Automating UVM to Tackle Insidious HW/SW Bugs." Presenters are David Murray, Duolog CTO, and Adam Sherer, director of verification solutions at Cadence. Murray kicked off the webinar by noting the importance of concurrent hardware/software development. "We want to make sure that software can be developed earlier, we want to make sure software is looking at a very accurate model of the hardware, and that we can also allow continuous hardware/software integration on an hourly or daily basis," he said.

HW/SW Interface: It's Harder Than it Looks

Murray showed a simplified "programmers view" of the hardware/software interface, took a deeper look at the IP level, and then showed a diagram of a hardware register that didn't look at all simple. "When you go into a register they are very complex," he said. Indeed, there are many attributes associated with registers - name, register reset, offset, access type, bitfield access, and bitfield reset, to name a few. A bitfield can have its own reset value and access types. It all adds up to a lot of information that needs to be managed, and that's where Sid can easily enter the picture.

"This [register] structure needs to be understood and implemented in the right way," Murray said. "Someone writes a spec, but the spec can be interpreted and implemented in a variety of different ways. There's a lot of duplication of information, a lot of manual processes, and communication between teams starts falling down."

It's very easy to make a small, subtle error that can cause weeks of effort in the lab. That's the nature of an "insidious" bug - "proceeding in a gradual, subtle way but with harmful effects," as Murray said. Dynamics that lead to insidious bugs include incorrect, unclear, or incomplete specifications; errors in translation to an implementation format; and mismatches (lack of synchronization) between different implementations.

UVM to the Rescue

The Accellera UVM 1.0 standard includes a register package, which provides an infrastructure that can verify the hardware/software interface. It comes with pre-packaged test cases, making it very easy to do hardware/software integration testing, Murray said. He walked through a detailed demo that showed UVM working in concert with the Cadence Incisive Enterprise Simulator to track down a bug in which someone changed a reset value without changing the spec.

"UVM caught the bug," Murray noted, "however, the spec is open to interpretation. There is a possibility we will get symmetrical errors. That means that people designing IP and people verifying IP can make the same mistakes, and it will not appear as an error -- you will get a false positive."

Automation is the solution, Murray said, and he discussed the Socrates Bitwise tool from Duolog, which provides a formal, executable specification of the hardware/software interface. "When you capture something with a register management tool like Bitwise, the quality of the specification is going to be much better, the interpretation is going to be automatic, and there's a correct by construction flow all the way down to implementation." In a follow-up demo, Murray showed how UVM in concert with Incisive and Bitwise was able to find an "insidious bug that was in the background the whole time."

Sherer said that Cadence provides a register generation capability for UVM, but Bitwise goes one step further by providing not just generation but static analysis to make sure the specification is captured correctly. "Customers are working with register environments with hundreds of thousands of register descriptions, far beyond the ability of a human to manage," he said. "I encourage our customers to look at automation for this specification and for UVM, and Duolog is a great choice."

The webinar is available here. Registration is required.

Richard Goering

Related blog post

Q&A: Duolog CTO Discusses SoC Integration Challenges

Sid graphic courtesy of Duolog Technologies

ARM TechCon: Q&A With Lip-Bu Tan, Cadence CEO

rgoering — Fri, 28 Oct 2011 04:14:00 GMT

What kind of collaboration does the semiconductor industry need now? How can we get more venture capital money into semiconductors? Is there a future for EDA in the cloud? These are a few of the questions asked by Simon Segars, executive vice president and general manager of ARM, of Lip-Bu Tan, president and CEO of Cadence, at a "fireside chat" (sans fireplace) at ARM TechCon Oct. 25. Excerpts from that conversation follow.

Segars: The theme of this show [ARM TechCon] is collaboration. What's your view of collaboration and what is it important to focus on?

Tan: There are two forms of collaboration. One is horizontal collaboration. An example is OpenAccess, which we contributed to the industry so we can have more interoperability between tool vendors, and help the customer. But the new area we really like is vertical [collaboration]. In some ways ARM TechCon does that, in some ways our CDN Live! does that, by being more focused on the customer. We are driving multiple collaborations between IP vendors, tool vendors, foundries, embedded software -- sometimes we even share locations together.

Segars: In your spare time you run a VC firm [Walden International]. As a VC investing money in semiconductor companies, you're a rare breed these days. Most of your colleagues seem to have given up on semiconductors. How do we get more money into semiconductor startups?

Tan: In 2001 roughly $2.5 billion was invested in semiconductors, either in the startup or expansion stage. That dropped to $1.2 or $1.3 billion in the past two years. This is almost a 60% drop. The other thing is, when we do a deal, we want co-investors who share the risk. I used to have 30 [co-investor] friends of mine but now it's down to less than 5. When you do the financing there are not many people to call.

Simon Segars (left) and Lip-Bu Tan (right) at ARM TechCon 2011

Meanwhile a lot of innovation comes from startups. It is very important to continue funding for startups. It's good for the industry. I'm on the board of GSA [Global Semiconductor Alliance] and we are looking at how we can help get some momentum going.

Segars: Do you think corporate venture funds can act in the same way that a VC does? VCs are looking for money, but we look at it as something we want to grow in our market. I think the motivation is different.

Tan: A corporation will drive some specified application or platform, so they will limit their focus and use their money for exactly the application they want to drive. It's good to have some balance with pure VCs. They bring some added value in terms of having a network, and they can broaden in terms of the applications or markets they serve. If you just focus on a particular application, then you limit the potential in terms of innovation.

Segars: We could come up with a number of reasons VCs don't find semiconductors interesting these days. It could be that social networking looks easier, and semiconductors are getting really expensive. The length of time to get a return is longer and exit options are fewer. What is the biggest factor and what might we do about it?

Tan: If you have $100 million revenue as a social networking company maybe you are worth $10 billion, and on the other hand if you have $100 million revenue [as a semiconductor company] you would be lucky to get a $500 million valuation. So there's a huge difference. That [social networking] is the easy money to make. We have to do the heavy lifting. We have to worry about the process node, the IP, the customer requirements, the design cycle, and then the tools to optimize the design.

Segars: The biggest products in the consumer market right now are smartphones and tablets. The problem is that people underestimate the technology that goes into building these products. They like using them, but they don't want to build them. Do you think this is an issue for the semiconductor industry? Engineering unfortunately looks hard, so somehow we've got to position hard work as fun at the same time.

Tan: We need to create some excitement and attract some of the engineering colleges. This is something I like to do in my spare time; I'm on the board of Carnegie-Mellon and on the advisory board to the dean at MIT and Berkeley. We're trying to create more excitement for the students.

In China, engineers are proud to be engineers. I go see a [government] minister and sometimes they give me a card that clearly says, engineer, and they are so proud and want to make sure you see that. Comparing that to here, how many in Washington are engineers? In China they really appreciate being engineers. I think we need to have that in this country.

Segars: When you look at companies to invest in, how do you judge the innovation that the team is bringing to you? You don't want something easily copied, and you want it to be defensible.

Tan: In the early days I was looking for proven entrepreneurs. Now I think it's more important to be addressing a big market. So first of all, look at the market potential, is it big enough to build a company? Secondly, you want to have some really good engineers. And most importantly, I ask, is the team really spending enough time with customers? Do they understand the pain points and the solution? 50% or 2X better is not good enough; you need to be at least 5X or 10X better and be sustainable and defensible.

Then you have to make sure it has the right funding. Don't fund too much - fund enough to clearly reach the milestones, so they can move on and progress as a company. With a smaller budget you become very creative and that's where your innovation comes in. If you only have a few million and you worry about next year's payroll, then you become very creative.

If you want to be a good VC, or a good CEO, you've got to see a movie called Moneyball. Watch that movie and even better get the book Moneyball by Michael Lewis. I love that book.

Segars: As a VC you must be looking at the costs of bringing something to market. The cost of building semiconductors is astronomical. Is there anything the industry can do structurally to lower costs?

Tan: For a startup, IP is very important. Secondly, startups need to strategically align with the right partners. They have to work with the foundry and they need to find one or two anchor customers. It is very important to define the product. Plan it wrong and you have no chance if there is only a 50% improvement.

The other part is that it's not just the hardware; the software can be very costly. Last year we launched EDA360. Basically it's about application-driven design, where hardware and software co-development and co-validation become critical. If you wait for the chip to come out to start developing software, the time will be too long.

Segars: For EDA tools specifically, we have our own compute clusters around the world, and it would be great to leverage the cloud and use it as we need it. Is that a way that you see EDA going?

Tan: We have been looking at the cloud and how we can provide service to startup companies that need that, and so we have a program in which we're doing that. But the issue is always security, for the customer and for us. Right now we're taking it one step at a time. We're saying, let's have our own secure, hosted environment, and over time explore what makes sense to big and small customers for using the cloud. Clearly the cloud is the way to go. As an EDA company we have to address that environment.

Audience question: VCs are looking at a 30X return. Why should an entrepreneur go to a VC? It seems like a horrible deal.

Tan: VCs add a lot of value through their networks. They can connect the dots. They have built multiple companies and have a lot of scar tissue, and they can help you so you don't have to walk through the same mistakes the other guys went through. Also, there are some opportunities you need money to do. If you want to build a multi-core processor it can take up to $100 million. Family or relatives may not be able to get you that far.

Audience question: This country has exported a lot of manufacturing, at one time because of the cost of labor. Do you see that coming back to the U.S.?

Tan: The cost difference in labor is narrowing a lot. In India, attrition is almost 25%, and where there used to be a 3X or 4X difference in terms of cost it's down to 2X now. I'm a U.S. citizen. I would love to have [manufacturing] come back. We need to have some manufacturing done here.

Richard Goering

Also about ARM TechCon 2011:

ARM TechCon Address: High Stakes at Low Process Nodes

Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

rgoering — Wed, 26 Oct 2011 14:00:00 GMT

You would expect a unique semiconductor product to have a unique software development environment. That is the case with the Xilinx Zynq-7000 family, an Extensible Processing Platform (EPP) that includes a dual-core ARM Cortex-A9 processor and a 28nm FPGA fabric. Today (Oct. 26, 2011) at ARM TechCon, Xilinx and Cadence are demonstrating an extensible virtual platform for the Zynq-7000, enabling software development and debugging before silicon is available.

Xilinx and Cadence announced today that they have teamed up to develop this extensible virtual platform, with general availability planned for Q1 2012. Clearly "extensible" is a key word here. The Zynq platform is extensible because developers can not only program the Cortex-A9, but can build custom logic, including peripherals and specialized embedded processors, into the FPGA fabric. The virtual platform is extensible because developers can extend it with SystemC transaction-level models (TLMs) that represent that custom logic. This extensibility occurs purely in software with no need to purchase a custom FPGA board.

Ready for more "extensibility?" The agreement extends the reach of commercial virtual platforms, which have thus far focused on ASICs and SoCs, into the FPGA realm. For Cadence, it extends a traditional ASIC focus into FPGAs. For both Cadence and Xilinx, it extends a silicon orientation into embedded software development. And it extends the conventional, silicon-centric view of EDA to software development and hardware/software integration, a shift described last year in the EDA360 vision paper.

A Quick Look at Zynq

Zynq was announced in March 2011 as the industry's first Extensible Processing Platform, "developed to achieve the levels of processing and compute performance required in high-end embedded applications targeting markets such as video surveillance, automotive driver assistance, factory automation, and many others." It promises the flexibility and scalability of an FPGA combined with ASIC-like performance and the ease of an ASSP.

The dual ARM Cortex-A9 processor is enhanced with the NEON floating-point unit, and comes with hardened memory controllers and peripherals including USB, Gigabit Ethernet, SD-SDIO, UARTs, and A/D converters. The Xilinx Series 7 programmable logic fabric uses the Artix-7 or Kintex-7 technologies, and provides up to 235K logic cells. The maximum frequency of the Zynq-7000 is 800 MHz. A high throughput interface between the processing subsystem and the programmable logic includes over 3,000 interconnections.

A detailed product brief is located on the Xilinx web site. The Xilinx Zynq press release noted that engineering samples will be available in 1H 2012.

A Quick Look at Virtual Platforms

Virtual platforms, or virtual prototypes, make it possible to create and debug software using a model of system hardware before that hardware is actually built. Earlier this year Cadence announced the Virtual System Platform, which is part of the System Development Suite, which also includes simulation, RTL emulation, and rapid prototyping.

The Virtual System Platform differs from previous commercial offerings in several key aspects:

It uses SystemC TLM-2.0 models, not a proprietary language.
It helps automate TLM model creation with a utility that can generate a TLM-2.0 template from IP-XACT input.
It uses the Incisive simulation kernel, and can thus be easily linked into the Cadence Incisive RTL simulation environment, or to acceleration and emulation with the Palladium XP Verification Computing Platform.
Software and hardware engineers can use familiar debug environments, with full visibility and controllability.
Multi-core hardware/software debugging makes It possible to view and control software execution in multiple cores.

The Zynq virtual platform is based on the Virtual System Platform and includes the capabilities mentioned above.

A Key Industry Innovation

So what portions of the Zynq-7000 EPP will the virtual platform represent? "Everything," said Jason Andrews, senior architect at Cadence. Most of the models were created by Cadence. The Cortex-A9 model, however, was developed by Imperas using their Open Virtual Platforms Fast Processor Model technology, and is available from the OVP website, http://www.ovpworld.org/. The base virtual platform is all TLM and "100 percent SystemC," as Andrews said. Users can extend the platform with their own TLM models, and users of the Incisive simulator can easily bring RTL models for legacy IP into the simulation.

Because the virtual platform is extensible, Zynq designers who use the FPGA fabric can develop SystemC TLM models and connect them to the base virtual platform. Even if a design team does not use the FPGA fabric, the virtual platform provides a way to develop software before the Zynq-7000 silicon is available - thus getting a potential jump on the competition.

Andrews noted that the Zynq virtual platform opens a high-volume potential for the emerging virtual prototype market, which has so far targeted mainly "tier one" OEMs. If the Zynq virtual platform can help bring virtual prototyping into the mainstream market, it will have a profound impact that will speed the development of integrated hardware/software systems, helping spur more innovation in the electronics industry.

You can learn more at http://www.cadence.com/zynq or see a demo at ARM TechCon Oct. 26-27 at Xilinx booth #207.

Richard Goering

ARM TechCon Address: High Stakes at Low Process Nodes

rgoering — Tue, 25 Oct 2011 23:30:00 GMT

The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In an Industry Address at the ARM TechCon conference Oct. 25, Hsu tackled some of the toughest challenges in IC design and showed how collaboration is providing solutions.

The demand for advanced process nodes is strong, Hsu noted. He pointed to the tremendous growth in the number of connected devices, the explosion of software "apps," and the proliferation of mobile devices. Customers in the consumer, computer and communications markets are moving ahead with 32/28nm and 22/20nm process nodes, Hsu said.

But these advanced nodes come with a cost. Fab investment in the 32/28nm node was around $3 billion, process R&D was around $1.2B, and a single system-on-chip (SoC) design may cost $50-$90 million. These costs will nearly double at 20nm. What nobody seems to talk about, Hsu noted, is the aggregate EDA tool development costs. He estimated these costs at $400-$500 million at 32/28nm and $800 million - $1.2B at 22/20nm.

Horizontal to Vertical

Hsu noted that the semiconductor supply chain has gone through a "horizontal segmentation" in which pure-play foundries have spun off, commercial EDA companies have emerged, and IP companies including ARM have arisen. Now that design has gotten really tough, what is needed is "vertical collaboration" that cuts across these horizontal segments. To illustrate this point Hsu showed a short video in which executives from Cadence, Broadcom, ARM and TSMC talked about collaboration between their respective companies.

One industry challenge that has responded to collaboration is low-power design. Five years ago, Hsu said, only a handful of customers with internal tool capabilities were doing advanced low-power designs. Even then, "it was all done at the gate level or transistor level as an afterthought," and many of the chips didn't work. Cadence developed a new methodology and worked with some 40 partners to refine it. The specification was later donated to the Silicon Integration Initiative (Si2). This was a reference to the Common Power Format (CPF), and you can read the latest update, from the Si2 Conference last week, here.

"Instead of a half-dozen high end customers, we enabled fabless semiconductor companies to have the same kind of [low power] capability," Hsu said. He went on to note that there are still low power challenges to solve, including analog/RF design. Hsu noted that Cadence has extended its low power methodology into the analog/custom arena, and he also spoke about the power analysis capability available with Cadence Palladium emulators.

An "exciting" new development that can help save power, Hsu said, is the clock concurrent optimization technology that Cadence acquired from Azuro (see my previous blog post for background). This technology combines clock tree synthesis and logic optimization into a single step, and it has been shown to increase performance and (not or!) decrease power and decrease area in SoCs with embedded ARM processors. With this technology, Hsu said, "we are breaking the traditional way of doing optimization and setting up a new paradigm."

20nm Challenges

Hsu cited a number of challenges on the road to 20nm, including 400 new design rules, layout-dependent effects, and double patterning. He showed how double patterning, which uses extra masks to make conventional lithography possible at 20nm, has impacts throughout the full-custom and digital implementation flows. He also showed some solutions that Cadence has developed to assist the colorized layout decomposition that double patterning requires.

At 20nm and below, FinFET devices have some area, frequency, and power advantages, Hsu said. He noted that Cadence is working with several foundries on this technology and already has a working FinFET Berkeley SPICE model.

Hsu noted that Cadence, TSMC, and ARM worked together to produce the first 20nm ARM Cortex-A15 tapeout, as announced last week. He also noted that Cadence and Samsung have worked together on a 20nm test chip tapeout. Finally, he pointed to an announcement today (Oct. 25) about a 32nm SoC designed at Ambarella in cooperation with Samsung and Cadence. The chip goes into a 16 megapixel HD digital camera that can take 30 pictures in one second (see Steve Leibson's blog post for more information). The chip achieves a 95% power savings during shutoff mode and a 60% power savings in sleep mode.

The Ambarella story is "just a tremendous collaboration," Hsu said. "If we hadn't done the collaboration work in this vertical way, a startup like this could never have done this kind of design."

Hsu also pointed to Cadence work with GLOBALFOUNDRIES on the DRC+ pattern-matching technology; work with lithography verification with TSMC; and finally, Cadence support for 2.5D and 3D-IC designs. "Vertical collaboration with all our partners is important," he concluded. "We are committed to helping our customers be successful."

ARM TechCon runs Oct. 25-27 in Santa Clara, Calif. Cadence presentations, activities and papers at ARM TechCon are summarized here.

Richard Goering

Photo by Joe Hupcey III

Designing ARM-Based SoCs? Don't Miss This Event!

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

Easing Mixed-Signal Design With the ARM Cortex-M0

Si2 Conference: New Directions for Low-Power Standards

rgoering — Tue, 25 Oct 2011 03:00:00 GMT

The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling, and the need for system-level power modeling including the impact of software. These presentations updated the work of the Si2 Low Power Coalition (LPC).

This blog post takes a brief look at the following presentations:

Qi Wang, technical marketing group director for low power solutions at Cadence and vice-chair of the LPC, discussed CPF 2.0 and steps towards IEEE 1801 interoperability.
David Hathaway, senior technical staff member of IBM and LPC TSG (technical steering group) chair, described recent work in "power contributor modeling."
Steve Schulz, Si2 president, gave a rousing call to action for getting to work on system-level power modeling - now.

These were just a few of the 15 presentations during the day-long conference, which also updated Si2's work on standards for process design kits (PDKs), design for manufacturability (DFM), and OpenAccess. Copies of presentation slides will be available on the Si2 web site this week.

At the conference, Schulz also presented Si2 Distinguished Service Awards to both Wang and Hathaway. Wang was honored for "many years of successful support and guidance of the LPC and the format working group," as well as his recent work in the IEEE P1801 working group. Hathaway was honored for his years of service in the LPC technical steering group as well as the working groups he's led.

CPF 2.0 and Interoperability with IEEE 1801

Wang noted some key milestones in the LPC Format Working Group, including:

CPF 2.0 released March 2011
CPF 2.0 tutorial webinar in May 2011
OpenLPM (Low Power Methodology) contributed to IEEE 1801 in June 2011
Interoperability Guide update approved by LPC in October 2011

He discussed CPF 2.0 highlights including macro-modeling improvements, new low-power IP blocks, and simulation enhancements. Modeling has been improved for low-power mixed-signal elements such as voltage regulators and analog ports. New low-power IP includes power and ground level shifters, bypass level shifters, and clamp cells for isolation. New verification features allow more control and functionality in simulation and emulation.

Much of the current focus, however, is on CPF interoperability with IEEE 1801. "We have to realize that even though these two formats are similar, there are fundamental differences," Wang said. "There are key methodology differences. Without resolving them there is no point in talking about format convergence."

CPF 2.0 added some new features to make interoperability easier. These include a more flexible power domain specification, a functional model definition, a hierarchical flow that allows virtual output/input ports, and state retention rule enhancements. Beyond CPF 2.0, OpenLPM is a converged power methodology designed to facilitate complete interoperability between CPF and IEEE 1801. It emphasizes the 1801 supply-set methodology over the older UPF 1.0 power/ground net-based methodology, deprecates incompatible UPF 1.0 constructs and methodologies, and extends 1801 to include commonly used CPF features.

The next CPF release, CPF 2.1, will have additional interoperability features and will have "potential extensions to enable system-level power intent specification," Wang said.

Power Contributor Modeling

Hathaway introduced some of the work done by the LPC Modeling Working Group in "power contributor modeling," particularly as it applies to leakage. He first noted that leakage power is highly variable across a PVT (process, voltage, temperature) range. Designers may want to do some early analysis when you don't know what the voltage is. What's needed is a PVT-independent way of representing the leakage.

The best approach, Hathaway said, is "don't put power in a power model, put descriptions of contributors into the power model." (A contributor could be something like channel leakage of devices, or gate leakage). The idea is to get a small set of contributors, each of which can be simulated - as opposed to the huge number of states that a conventional modeling approach would require.

Many design flows do something similar, Hathaway said - such as estimating leakage by looking at total device width. The LPC is looking for a standardized approach, but not necessarily a new standard; the working group is working on a proposal that would enhance the Liberty library syntax.

Moving Up to Software

Schulz' talk was titled "The Next Frontier in EDA Standards," and his discussion of the "next frontier" was all about power. He noted first that power is a multi-dimensional problem because it has so many interactions and tradeoffs with other concerns. Invoking the 80/20 rule, he said that the "greatest opportunity" to reduce power is "at the higher levels, before you've made some of the committed decisions that lock you into a certain tradeoff."

"Software is a fundamental and primary driver of dynamic power consumption, and that's something we're going to have to take seriously as an industry," Schulz said. He noted, however, that "you're not going to simulate every detail of an application, so what we have to do is think about a smarter way of capturing the most important parts of that information, and communicating that back from the software world into the [hardware] world we live in."

What's needed, he said, is a system-level specification of power intent, and "part of that is already in the early stages for the next revision of CPF, because the idea is to move up to the ESL [electronic system level] stage. That is very important work and we need input, we need help in figuring out the smart way to do that."

"I don't know when you think this kind of capability will be needed in the industry, but if you think it's less than 5 or 6 years out, then we're late," Schulz concluded. "We need to get started now."

For another report on the Si2 Conference, see my previous post on DFM standards.

Richard Goering

GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

rgoering — Mon, 24 Oct 2011 04:00:00 GMT

DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference, GLOBALFOUNDRIES has donated DRC+ data structures to the Si2 DFM Coalition (DFMC), which will incorporate this technology into the emerging OpenDFM standard.

Currently aimed at 28nm, DRC+ is a pattern-based methodology that can be run "in design" by chip design teams well before tapeout. It goes beyond traditional design rule checking (DRC) by using a 2D pattern-matching approach to identify layout patterns that could be difficult to manufacture. As noted in a previous Industry Insights blog post, DRC+ rules are comprised of a rule detracting pattern to avoid and a recommended DFM rule to follow.

Although it doesn't sacrifice accuracy, DRC+ can be hundreds or thousands of times faster than traditional DRC or simulation. In an example cited in a recent blog post on in-design DFM signoff, a 300micron² block that was designed in the Cadence Virtuoso environment was checked using DRC+. It took around 5 seconds to find 23 hot spots and fix all of them. Running model-based simulation on the same block took around 8-10 minutes.

DRC+ uses a library of yield-detracting patterns and DFM rules. EDA tools consume those libraries and run DRC+ in pushbutton mode. Some tools that support DRC+, including the Cadence Virtuoso and Encounter environments, offer automatic fixing, as shown below:

Adding to an Open Standard

OpenDFM, meanwhile, is an open-source, extensible format that describes verification intent for leading process nodes, including conditional rules and ranges of acceptable values. Cadence has implemented OpenDFM rules in its Physical Verification System. Si2 released OpenDFM version 1.1 in May 2011.

At the Si2 Conference, Jake Buurma, vice president for West Coast operations for Si2, noted that OpenDFM checks patterns, not design rules. Why? Design rules, he said, are prescriptive - they result in a "pass" or "fail," but designers can't find marginal or robust patterns. Patterns, on the other hand, are descriptive. A pattern-based verification approach can improve marginal patterns and recommend robust patterns.

Buurma said that OpenDFM currently has a library of around 100 patterns now and wants to increase it - and that's where DRC+ comes in. "DRC+ will provide the infrastructure for thousands of patterns," he said.

What GLOBALFOUNDRIES is Donating

Vito Dai, senior member of technical staff for DFM at GLOBALFOUNDRIES, described the rationale and history behind DRC+. He noted that conventional design rule checking does not guarantee yield due to context-dependent effects. Designers can use model-based simulation or recommended design rules, but this brings printability verification into the design flow. DRC+ is an alternative that makes it possible to identify patterns that cause DFM problems - and it can run 10,000 times faster than simulation, he said.

What exactly is GLOBALFOUNDRIES donating? "Today, GLOBALFOUNDRIES is announcing the donation to Si2 of the complete set of data structures for DRC+ patterns, including the XML representation we use, XSD files, examples and user documents, so this capability can be standardized in the industry," Dai said.

Dai noted that the foundry intends to extend DRC+ up to 40nm and down to 20nm, with support for double patterning at 20nm. He also noted that GLOBALFOUNDRIES uses the Cadence pattern classification tool. At this time, he said, the four leading IC place and route vendors all support DRC+.

"Cadence is a strong supporter of Si2's DFMC program, as well as the OpenDFM technology," said Ken Potts, product marketing director at Cadence. "As a co-inventor of DRC+ and an implementer of OpenDFM in our physical verification tools, Cadence is working hard to make sure designs can be verified at advanced process nodes."

Richard Goering

For Further Information

Blog post: How DRC Plus Makes DRC Easy at 28nm

Blog post: "In Design" DFM Signoff - the Inside Story

Archived webinar: DRC+ Now: Early DFM Signoff in the Custom Implementation Process

Archived webinar: DRC+ Now: Early DFM Signoff in the Digital Implementation Process

Easing Mixed-Signal Design With the ARM Cortex-M0

rgoering — Wed, 19 Oct 2011 13:00:00 GMT

The ARM Cortex-M0 processor core is increasingly finding its way into analog/mixed-signal applications in such areas as automotive, RF, medical, power management, and display drivers. For many applications, a flexible and scalable architecture with an embedded processor is a far better solution than building custom logic to provide digital control. But using embedded processors in mixed-signal designs poses some challenges, and it requires a comprehensive solution.

To help mixed-signal designers who are using or contemplating the use of the Cortex-M0, ARM and Cadence are co-presenting a Sponsored Session at ARM TechCon Tuesday, Oct. 25 (see my previous blog post for a general overview of the conference). To get some background on the challenges and requirements of mixed-signal design with an embedded processor, I spoke to Mladen Nizic, engineering director at Cadence and a presenter at the session. Following are some perspectives that emerged from our discussion.

What does the ARM Cortex-M0 provide?

The Cortex-M0 is the smallest, lowest power, and most energy-efficient ARM processor available. Its small area, compact code, and low power and 32-bit performance make it very attractive for many mixed-signal applications. The core has just 12K gates (in its base configuration), uses set of just 56 instructions and consumes as little as 3 µW/MHz (0.003 mW). Further information is available at the ARM web site.

Why are designers using the Cortex-M0 in mixed-signal devices?

Analog/mixed-signal devices increasingly require digital control. Digital logic may be needed to control inputs and outputs, drive controllers, run display drivers, process and filter signals, and perform many other tasks. At advanced process nodes, digital control is also increasingly needed for self-calibrating analog circuits.

Traditionally, mixed-signal designers start implementing digital functionality with custom logic, and then quickly find it inefficient due to the increasing amount of digital logic they need to design and integrate. A mixed-signal flow with an integrated capability for synthesis and place and route helps create and implement digital controls more efficiently. Furthermore, using an architecture with an embedded processor such as the M0 brings greater flexibility, since it's a lot easier to modify or write new code than to build new logic whenever functionality changes are required.

What challenges arise when mixed-signal designers adopt an embedded processor?

Designers have to put analog and digital circuits on the same chip and verify that they work together properly. Implementing the core itself is straightforward, and the design methodology predominantly depends on what needs to be integrated with it. The first challenge is functionally verifying the design. IP blocks need to be verified separately and in combination with each other. To achieve this in a reasonable period of time, engineers need to go beyond traditional SPICE simulation and employ faster simulation and verification methodologies.

To minimize power consumption, low power designs techniques are often used in mixed-signal designs. This requires low power verification, implementation, and analysis capabilities in the design flow, and that becomes more challenging in a mixed-signal environment.

Minimizing area is another key challenge that requires the tight integration of analog and digital functionality and efficient chip floorplanning. The correct placement of IP blocks is crucial in order to avoid signal interference, protect sensitive analog circuitry, optimize area, and save power.

Chip integration and signoff with silicon predictability is another challenge. Often a combination of parasitic mixed-signal simulation and static timing analysis is required to confidently sign off on the design.

What kind of flow is needed to overcome these challenges?

A unified mixed-signal flow that encompasses both analog and digital design for verification and implementation is needed. On the verification side, an integrated simulation engine capable of handling different levels of abstraction is required, supported by behavioral modeling techniques.

On the implementation side, a mixed-signal flow that uses a common database for design data and constraints enables optimal floorplanning and chip integration, with visibility into mixed-signal IP blocks for accurate signoff. The Cadence mixed-signal solution offers a highly integrated flow comprising of the production-proven Virtuoso, Incisive and Encounter platforms, and is well suited for these kinds of designs.

What can attendees expect at the ARM TechCon Sponsored Session?

ARM and Cadence will jointly present an overview and discuss the advantages of the Cortex-M0, describe verification and implementation flows for designing mixed-signal applications with the core, and outline available physical libraries and IP.

This is an ideal session for anyone planning on using Cortex-M family, or already designing with it and looking to enhance their mixed-signal methodology, or just wanting to learn something new.

Some further information about the Sponsored Session

The one-hour session will be held Tuesday, Oct. 25, at 2:00 pm in room C at the Santa Clara Convention Center. In addition to Mladen Nizic, presenters include Dominic Pajak, Embedded Segment Manager at ARM, and Raviraj Mahatme, platform marketing manager at ARM. Further information about this session and other Cadence activities at ARM TechCon is available here.

Richard Goering

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

rgoering — Tue, 18 Oct 2011 13:00:00 GMT

Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will optimize Cadence's design and verification flows for advanced ARM processors. This post will look at what some of those optimizations involve and how they will help SoC designers who use ARM Cortex processors.

In September 2010, Cadence announced an unusually deep and early collaboration with ARM to develop a reference methodology for customers seeking early access to the multi-core Cortex-A15 processor. I blogged about this collaboration last fall. The collaboration resulted in an optimized reference methodology that helped give Texas Instruments, an early Cortex-A15 licensee, a head start in its development work.

The new agreement includes the Cortex-A9 as well as the Cortex-A15. The multi-year agreement will provide ARM development teams with Cadence Silicon Realization products and access to Cadence design services. It will also result in an optimized Cadence Encounter Digital Implementation flow and Incisive verification flow for mutual ARM/Cadence customers, as described below.

Adding Knowledge

To understand what the agreement means for Cadence customers who are ARM licensees, I talked to John Murphy, director of strategic business alliances, and Rob Lipsey, a distinguished Cadence engineer who has been working with ARM. The bottom line, said Murphy, is that "because of our knowledge and its codification into heuristics in our tools, they [customers] are going to be able to lower their design risk and speed their time to market."

Murphy said this knowledge was gained through months of close work with ARM, starting with early access to RTL code. This led to "fine tuning" that will help Cadence Encounter users optimize Cortex designs for power, performance, and area. Lipsey cited several examples, including optimizing certain kinds of case statements in synthesis, clustering registers more closely with clock gating cells, concurrent optimization of synthesis and physical implementation, and handling sub-optimal mux structures in synthesis.

The work with ARM also led to new Encounter Digital Implementation System capabilities that help designers avoid timing bottlenecks. CPU designs, Lipsey explained, have cells that fan out signals to many end points. The Encounter Digital Implementation System can help ARM Cortex users attack a potential bottleneck at the right location, making it possible to optimize many points in the design concurrently and speed up run time.

"The value add in terms of knowledge cannot be understated," Lipsey said. "When a new customer loads up a Cortex-A9 or a Cortex-A15 design and it's not meeting timing, we know where the design could get stuck. For example, maybe there are paths to memory that should not be critical. We have knowledge of where you need to crank on the design and where you don't. Some of that is built into our tools."

The collaboration also involved some development work in high-frequency clock tree optimization, and that's part of what led to the subsequent acquisition of Azuro by Cadence, which I blogged about recently. The clock concurrent optimization technology developed by Azuro combines clock tree synthesis and physical optimization into a single step. It has been shown to improve performance and to reduce power consumption and area for SoC designs with ARM Cortex processors. Clock concurrent optimization (ccopt) is now a technology add-on for Encounter, and the ccopt technology is well on its way to full integration within the Encounter Digital Implementation System.

On the verification side, the collaboration resulted in a significant simulation speedup for advanced ARM processors. Cadence tuned its Incisive Enterprise Simulator to deliver performance improvements of more than 2X on the Cortex-A15, and more than 8X on the Cortex-A5. Cadence also worked with ARM on testbench optimization.

Into the Field

The "vast experience" gained from the ARM-Cadence collaboration extends beyond optimized tools and into the field organization and services. "We have a lot of people inside Cadence who are experts on the [ARM Cortex] design and are able to go out and leverage that knowledge across many different customers," Lipsey said. This knowledge includes Cortex-A15 debugging, always a challenge for advanced multi-core processors.

The deep collaboration with ARM is a sign of things to come, noted Y.T. Lin, vice president of research and development at Cadence. "Deep collaboration is needed for high-performance designs such as CPU cores," he said. "By working together we can understand what they are trying to achieve from a design perspective, and we can develop the latest [EDA] technology to accommodate their needs."

Further information about Cadence tool support for ARM Cortex processors, as well as 28nm and 20nm design flows, will be available at the ARM TechCon conference next week. A 20nm whitepaper from Cadence is available here.

A new ARM resource page is available at Cadence.com. It includes further information about the recent collaborative work between Cadence and ARM on tool support for advanced Cortex processors. This page also describes the Cadence Silicon Realization and System Realization flows for ARM processors, lists relevant webinars and events, cites Cadence news related to ARM, and provides links to information on the ARM web site.

Richard Goering

“Assertion Synthesis” Webinar: Questions, Answers About NextOp BugScope

rgoering — Mon, 17 Oct 2011 13:00:00 GMT

You know a webinar is hot when the questions just keep rolling on in from the audience and go well into overtime. Such was the case in a newly archived Cadence webinar titled "Automate Assertion Generation for Simulation, Formal and Emulation Flows." The webinar showed how "assertion synthesis," as provided by Cadence partner NextOp Software, can expedite assertion-based verification, reveal functional coverage holes, and increase verification observability.

The Oct. 13 webinar was presented by Joe Hupcey, product marketing director at Cadence, and Yuan Lu, CTO of NextOp. It is part of an ongoing functional verification webinar series that will extend into November and December.

Hupcey started with a brief review of ABV terminology, noting that assertions express desired behavior of a device under test (DUT), while cover statements express the desired reachability of states in the DUT and the environment. Both are subcategories of "properties," which are statements about the behavior of a design and its environment. The value of ABV, Hupcey said, is two-fold - significant time savings, and higher design quality. He noted that ABV can result in a 25% faster time to market.

Generating Assertions

So, why isn't ABV in broader use? One reason is that assertions are difficult to create and maintain due to syntax complexity. Manual coding typically takes 20 minutes to 1 hour for each assertion. It is challenging to debug failed assertions, and easy to fall short of the number of assertions needed. Thus, the ability to automatically generate assertions through assertion synthesis is a tremendous benefit.

One tool that automatically generates assertions is Automatic Formal Analysis (AFA), which is included with the Cadence Incisive Formal Verifier and Incisive Enterprise Verifier. This is a pushbutton solution that generates assertions for the most common design errors from the DUT. However, it only supports basic white box assertions. As Hupcey noted, the BugScope product from NextOp goes further.

Yuan Lu took over from here and noted that BugScope creates both high-quality white box assertions and high-quality functional coverage goals. It leverages simulation to create assertions automatically. Lu said that BugScope can produce assertions for 1-10% of RTL lines, without duplicating RTL or other properties. Assertions offer a low runtime overhead and can be leveraged in simulation, formal verification, and emulation flows.

As shown in a demo in the webinar, BugScope has three basic steps:

Simulate using the BugScope PLI. Input is the testbench, plus test vectors and RTL. Output is a NextOp database file for each simulation run.
BugScope post processing. Input is NextOp databases plus RTL. Output is BugScope-generated properties.
Users manually classify properties as assertions or cover statements. BugScope supports SystemVerilog assertions (SVA), Property Specification Language (PSL), or Verilog.

The diagram below shows how BugScope works in a metric-drive verification flow with the Cadence Incisive platform. Basically, users start with a UVM testbench in the Incisive Enterprise Simulator (IES) and run BugScope to synthesize assertions and cover statements. These can be brought into simulation, formal or emulation flows, and can target code coverage in Incisive Enterprise Verifier (IEV). Finally, results are displayed in an executable vPlan (verification plan) in Incisive Enterprise Manager.

Probing Questions

Here are a few of the many questions that were asked by attendees - and answered by Lu -- during the webinar.

Q: Does the tool have the capacity to do an entire chip in one shot, or is it done in pieces?

A: The tool is module based, but you can launch as many modules as possible to the server farm.

Q: If the RTL code has a bug, and the RTL is incorrect, will NextOp create an incorrect assertion on incorrect behavior?

A: If you have good behavior in your simulation and you still have a bug that was never activated, hopefully our cover properties will show that. If a bug is activated but does not propagate to the checker, hopefully we can discover the cover property that blocks this bug. When we give you a property you will probably realize something is wrong with the RTL.

Q: Does BugScope require a testbench or can it just get assertions from RTL?

A: We require a testbench. If there's no testbench, you can use [Cadence] AFA or manual generation.

Q: How complex are the assertions? Are they structural or operational?

A: We are focusing on white box assertions and we typically generate assertions that take one to two cycles. We don't generate long temporal assertions for now. We have a pipeline to add temporal assertions in future versions of the tool.

Q: If I'm not familiar with assertions, can I interpret the output of the tool?

A: We are not targeting experts, and people who are not used to assertion languages can use the tool. The output format is very much like Verilog.

Q: Do you synthesize assertions for design behavior not simulated by any test?

A: In such an area we cannot give you assertions, but we can tell you this area was never covered.

Parting Words

As Hupcey said at the end of the webinar, "ABV is extraordinarily powerful. And assertion synthesis with BugScope automates the front end of this challenge. It creates the assertions and the coverage and identifies pretty well hidden corner cases in the process." Further information, including a whitepaper, is available at the NextOp web site. To view the webinar, available free to Cadence Community members, click here.

Richard Goering

Related Cadence Community blog posts

Q&A: NextOp CEO Describes "Assertion Synthesis"

Video: Interview With NextOp CEO Yunshan Zhu on Assertion-Based Verification (ABV) With "BugScope"

Connections Partner NextOp on Assertion Synthesis and Assertion-Based Verification (ABV) with "BugScope"

Video: DVCon and DVClub Case Study: NextOp's BugScope for Assertion-Based Verification (ABV)

Video: DAC 2011 Update From NextOp CEO Yunshan Zhu

Video: DVCon 2011 Update From NextOp CEO Yunshan Zhu

DVClub: Verification Users Discuss Assertion Challenges and Solutions

Renamed Si2 Conference Updates EDA Standards

rgoering — Thu, 13 Oct 2011 13:00:00 GMT

The Silicon Integration Initiative (Si2) standards organization has held 15 previous OpenAccess Conferences. This year Si2 is calling their annual event, scheduled for Thursday, Oct. 20, the "Si2 Conference." In addition to OpenAccess, the one-day event will provide updates on emerging standards for design for manufacturability (DFM), low power design, and process design kits (PDKs). The new conference name reflects that fact that all these efforts are increasingly interrelated.

The Si2 Conference will be held in Santa Clara, California, from 8:30 am to 7:30 pm. Highlights of the agenda include the following:

"The Next Frontier in Standards," a talk by Si2 president and CEO Steve Schulz. (A report on his talk at last year's conference is located here.)
Keynote speech on SoC Realization by Ajoy Bose, CEO of Atrenta.
Session on DFM standards, which will update activities of the Si2 DFM Coalition. This session also includes a talk on DRC+ by Luigi Capodieci of GLOBALFOUNDRIES and presentations from LSI and Si2.
Session on PDK standards, including the work of the OpenPDK Coalition. In addition to speakers from IBM and STMicroelectronics, Barry Nelson of Cadence will provide an update of the SCC (symbol, CDF and callback) working group.
Session on low power standards, including the work of the Low Power Coalition. Qi Wang of Cadence will discuss new advancements in CPF 2.0 and the path to interoperability. Speakers are from IBM and Calypto will discuss power modeling and optimization.
Session on OpenAccess. Johannes Grad of Cadence will illustrate what's new with OA 22.42. Speakers from Entasys, Mentor Graphics, and SpringSoft will discuss their use of OpenAccess.

The agenda also includes a lunch sponsored by Cadence, as well as demos and a reception starting at 5:40 p.m.

I've attended most past OpenAccess conferences and have always found them to be interesting and relevant. This is a good event for anyone concerned with EDA interoperability -- which, in these days of skyrocketing complexity, is just about anyone who is developing or using EDA tools.

A detailed agenda is located here: http://www.si2.org/?page=1489

You can register on line here: https://www.si2.org/openeda.si2.org/si2_store/index.php#c1

Richard Goering

Industry Insights

Digital and Analog Verification – Round Peg in a Square Hole?

Customer, Partner DFM Concerns Spur New Methodologies

Webinar Report: New Methodology Revs Up Code Coverage Analysis

Panelists: Bridging the Gap Between Analog and Digital Design

Whitepaper: Verification Performance is More Than Raw Simulation Speed

Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

SPIE Papers Showcase DFM and Lithography R&D

Webinar Report: Power-Aware Mixed-Signal Verification

Q&A: Frank Schirrmeister Updates Status of System-Level Design

Webinar Report – New Approaches to Mixed-Signal Verification and Assertions

“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language

Update on OrCAD Free and Paid “Apps” – What is Available Now

CDNLive! Silicon Valley – Agenda Set, Registration Open, $99 Deal

Webinar Report: Solving Mixed-Signal Power Grid Challenges

Open NAND Flash Interface (ONFi 3.0) – Faster Throughput for SoC Designs

The Denali Memory Report has Returned!

User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

All Things Analog – Video Interviews with Experts

Top Ten Cadence Community Blog Posts of 2011

2011 EDA Standards Update and 2012 Forecast

Synthesis User Panel: Power Dominates Front End Design

An Update on the JEDEC Wide I/O Standard for 3D-ICs

How Logic Synthesis is Changing

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

Archived Webinar: Using Scoreboards With Formal Verification

Accellera-OSCI Union Completed – What It Means for EDA Standards

Free, On-Demand “Tech on Tour” – Digital, Custom/Analog, and PCB

ARM TechCon Paper: Early Architectural Planning With a Digital Implementation Flow

Want Better EDA Tool Performance? How Cadence IT Can Help

ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development

ARM TechCon Paper: Why DRAM Latency is Getting Worse

Video: Why TSMC Cares About System-Level Design

Archived Webinar: Which Verification Coverage Metrics to Use When

EDA “Nobel Prize” Goes to Algorithmic Pioneer

IEEE Revises SystemC for 2011 – What’s In It For Users

ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs

Archived Webinar: Bringing SystemC and C/C++ Models into UVM

ARM TechCon Highlights Roundup – Blogs, Videos, and More

ARM TechCon Paper: “Tips and Tricks” for Cortex-A15 Designs

Webinar: How to Stop “Insidious” Bugs at the HW/SW Interface

ARM TechCon: Q&A With Lip-Bu Tan, Cadence CEO

Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

ARM TechCon Address: High Stakes at Low Process Nodes

Si2 Conference: New Directions for Low-Power Standards

GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?

Easing Mixed-Signal Design With the ARM Cortex-M0

Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

“Assertion Synthesis” Webinar: Questions, Answers About NextOp BugScope

Renamed Si2 Conference Updates EDA Standards