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Industry Insights Blog

EDPS 2014 Keynote: What Intel Needs from Pre-Silicon Prototyping

Pre-silicon prototyping is a new technology for many companies, but at Intel, it's important enough to warrant a dedicated support team. At the Electronic Design Process Symposium ( EDPS 2014 ) on April 17, Chris Lawless , director of pre-silicon...  Read More »
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Keynote: EDA “MOOC” Opens Door to a Planet of Talent

Participants at the recent CCC/SIGDA Workshop on Extreme Scale Design Automation discussed various ways to motivate students to consider EDA-related careers. And few approaches have cast a broader net than an EDA-related Massive Open Online Course taught...  Read More »
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“Extreme” Scale EDA Workshop Discusses Research and Funding Priorities

Seeking to empower the future of EDA, around 30 EDA researchers from academia and industry met at the CCC/SIGDA Workshop on Extreme Scale Design Automation in Tampa, Florida in late February 2014. Participants were invited to articulate a vision for the...  Read More »
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IEEE Panel Charts “Top SoC Design Challenges”

What are the top ten challenges in system-on-chip (SoC) design today? Can virtual platforms, cloud computing, and fully depleted silicon-on-insulator (FD-SOI) be part of the solution? Experts discussed these points April 8, 2014, in a panel organized...  Read More »
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Videos, DVCon 2014 Papers – Formal Verification “Apps” Move to SoC Level

Formal verification is a well-accepted technology for block-level verification, and it's now moving up to the system-on-chip (SoC) level. That's the message behind two paper sessions and two poster presentations at the recent DVCon 2014 conference...  Read More »
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CDNLive 2014 Paper: HP Engineers Road-Test Cadence Incisive vManager Solution

If you really want to know how a new EDA product works, listen to someone who has thoroughly tested and used it. Verification engineers and managers got a chance to do just that at CDNLive Silicon Valley 2014 , where a Hewlett-Packard engineer described...  Read More »
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Stan Krolikoski Video: New IEEE Working Groups Pursue EDA Standards

The IEEE has always been regarded as the final word when it comes to standards that impact electronics design. It is thus significant that several new EDA-related IEEE working groups have recently been formed (or re-activated), drawing on contributions...  Read More »
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Q&A with Nimish Modi: Going Beyond Traditional EDA

Over the past few years, Cadence has evolved from its role as a traditional EDA tool provider to become a system development partner that is enabling the design of the end products that impact our daily lives. In this interview, Nimish Modi, senior vice...  Read More »
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DVCon 2014 Video: HP Engineers Apply “Test Driven Development” to UVM-e

Test-driven development ( TDD ) and unit testing are methodologies that can greatly shorten functional verification time and increase quality. Engineers at Hewlett-Packard are currently applying these techniques with UVM- e (Universal Verification Methodology...  Read More »
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Electronic Design Process Symposium (EDPS) Reviews Design Flow Challenges and Solutions

If you want to understand how chips and systems are designed today, and what challenges lay just around the corner, there's no better place than the Electronic Design Process Symposium (EDPS) in Monterey, California on April 17-18, 2014. Now in its...  Read More »
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