Panelists: Bridging the Gap Between Analog and Digital Design
By Richard Goering
on February 1, 2012
Analog and digital designers have lived in separate worlds for a long, long time. They use different methodologies and tools, and while digital design is heavily automated, analog design is not. But mixed-signal integration will force this gap to narrow...
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Filed under: Industry Insights, SoC, Analog, verification, IP, Mixed-Signal, mixed signal, Panel, AMS, DesignCon, Nizic, Cadence, Synopsys, analog IP, digital, microcontrollers, analog comeback, analog automation, Brian Bailey, analog design, IPextreme, analog panel, Savage, A/MS, Cypress, Tanner
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Whitepaper: Verification Performance is More Than Raw Simulation Speed
By Richard Goering
on January 31, 2012
RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises...
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Filed under: Industry Insights, Multicore, verification, Functional Verification, Incisive, Simulation, multi-core, whitepaper, assertion-based verification, debugging, simulator performance, RTL simulation, white paper, Incisive Enterprise Simulator, scaling, simulation speed, gate-level simulation, reseeding, elaboration, regressions
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Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon
By Richard Goering
on January 30, 2012
DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore...
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Filed under: Industry Insights, DVCon, low power, TLM, verification, Mixed-Signal, System C, mixed signal, Functional Verification, UVM, NASCUG, emulation, coverage, UVM-MS, debugging, prototyping, mixed-signal verification, DVCon 2012, HW/SW co-verification
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SPIE Papers Showcase DFM and Lithography R&D
By Richard Goering
on January 26, 2012
Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational...
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Filed under: Industry Insights, lithography, DFM, CMP, IP, EUV, Double Patterning, OPC, 28nm, variability, pattern matching, yield, source mask optimization, 20nm, 22nm, Cadence, manufacturability, layout, leakage, LDE, in-design signoff, metal fill, layout-dependent effects, SPIE, computational lithography, SADP, context, model calibration, RET, hotspot
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Webinar Report: Power-Aware Mixed-Signal Verification
By Richard Goering
on January 25, 2012
Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption...
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Filed under: Industry Insights, low power, Virtuoso, CPF, Analog, Mixed-Signal, mixed signal, low-power, AMS Designer, AMS, Power, SPICE, SystemVerilog, webinar, assertions, analog/mixed-signal, SVA, analog assertions, PSL, Property Specification language, parasitic flow, Verilog, Bhattacharya, mixed-signal assertions, mixed signal simulation
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Q&A: Frank Schirrmeister Updates Status of System-Level Design
By Richard Goering
on January 22, 2012
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic...
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Filed under: Industry Insights, ESL, SystemC, RTL, High-level Synthesis, HLS, TLM, virtual platforms, verification, prototypes, embedded software, software, debugging, virtual prototoyping, System Development Suite, rapid prototyping, system-level design, hardware/software co-design, system level design, Schirrmeister, FPGA-based prototypes, Frank Schirrmeister, SLD
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Webinar Report – New Approaches to Mixed-Signal Verification and Assertions
By Richard Goering
on January 19, 2012
Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between...
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Filed under: Industry Insights, Virtuoso, Analog, Mixed-Signal, mixed signal, AMS Designer, AMS, SPICE, SystemVerilog, webinar, assertions, analog/mixed-signal, SVA, analog assertions, PSL, Property Specification language, parasitic flow, Verilog, Bhattacharya, mixed-signal assertions, mixed signal simulation
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“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
By Richard Goering
on January 17, 2012
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams...
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Filed under: Industry Insights, SystemC, low power, specman, verification, UVM, MDV, Amazon, acceleration, SystemVerilog, e language, UVM-MS, mixed-signal verification, Sherer, multi-language, verification book, UVCs, Advanced Verification Topics
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Update on OrCAD Free and Paid “Apps” – What is Available Now
By Richard Goering
on January 16, 2012
Last year Cadence announced the OrCAD Capture Marketplace , a web-based capability within the OrCAD Capture environment that provides an on-line store with free and paid plug-in tools, or "apps." Since then the list of available apps for OrCAD...
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Filed under: Industry Insights, PCB Design, PCB, applications, OrCAD Capture Marketplace, schematics, panelization, nsWare, SymbolGen, PCB Editor, FloWare, Capture, OrCAD apps, PCB apps
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CDNLive! Silicon Valley – Agenda Set, Registration Open, $99 Deal
By Richard Goering
on January 12, 2012
CDNLive! Silicon Valley, the Cadence user conference for the U.S., is set for San Jose, California March 13-14 at the DoubleTree Hotel. An agenda and registration information are now available on line , and there's a special "early bird"...
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Filed under: Industry Insights, CDNLive! Silcon Valley, EMEA, CDN Live!, Designer Expo, CDN Live
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