DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions
By Richard Goering
on May 21, 2013
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference ( DAC 2013 ) in Austin, Texas June 3-5. At last count nearly 50 customer...
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Filed under: Industry Insights, DAC, SoC, verification, AMS, analog/mixed-signal, Cadence, Tensilica, custom/analog, System Development Suite, Design Automation Conference, EDA360 Theater, semiconductor IP, user presentations, Cosmic Circuits, DAC 2013, Cadence Theater, Forte, customer, partner, SoC IP
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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis
By Richard Goering
on May 20, 2013
Cadence this week (May 20, 2013) announced the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure...
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Filed under: encounter timing system, SSTA, Multicore, parallelism, static timing, STA, multi-threading, multi-core, Cadence, signoff, ETS, Molina, distributed processing, timing analysis, Tempus, parallel computing, parallelized computation, timing closure, parallel processing
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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
By Richard Goering
on May 16, 2013
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information...
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Filed under: Industry Insights, DAC, chip estimate, SoC, IP, IC Design, Cadence, Design Automation Conference, IP Talks!, ChipEstimate.com, semiconductor IP, silicon IP, IP Talks, DAC 2013, Sean O'Kane
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DAC 2013: User Perspectives on System-Level Verification
By Richard Goering
on May 15, 2013
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design...
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Filed under: Palladium, ESL, virtual platforms, Freescale, AMD, IBM, Incisive, Verification IP, VIP, acceleration, emulation, Cadence, FPGA prototyping, VSP, RPP, virtual prototyping, System Design Suite, system-level design, Frank Schirrmeister, in-circuit acceleration, DAC breakfast, DAC panel, DAC 2013, system-level verification, system to silicon, DAC:
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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
By Richard Goering
on May 13, 2013
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer...
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Filed under: low power, Virtuoso, UPF, CPF, Conformal, Analog, verification, Functional Verification, Incisive, Convergence, mixed-signal verification, IEEE 1801, Maxim, power formats, UPF 2.1, 1801-2013, CPF user, Kamran Haqqani, 1801-2009, Haqqani
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Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story
By Richard Goering
on May 5, 2013
There is no doubt that Joe Costello, the first Cadence CEO, knows how to tell a compelling company story. Under his charismatic leadership, Cadence experienced explosive growth after its formation in 1988, becoming the largest EDA company within just...
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Filed under: Industry Insights, EDAC, EDA Consortium, Cadence, Hogan, Jim Hogan, VCs, Costello, painkillers, emerging companies, company story, entrepreneurs, slides, EDA startups, venture capitalists, Oasys, Orb Networks, Joe Costello
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Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
By Richard Goering
on May 1, 2013
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation...
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Filed under: Industry Insights, Encounter, EDI, digital implementation, CDNlive, CDN Live, optimization, GigaOpt, CDNLive 2013, EDI 13.1, path balancing, AAE, route-driven optimization, Benzel, path compaction, GigaOpt preRoute, EDI System, Jack Benzel, EDI System 13.1, buffering, layer selection, Advanced Analysis Engine, Avago, re-buffering
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EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges
By Richard Goering
on April 29, 2013
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to...
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Filed under: EDA, Oracle, FinFets, SPICE, 20nm, Semiwiki, Nenni, FinFET, EDPS, 14nm, transistors, RC, 16nm, BSIM-CMG, Cgx, capacitance, body effect, Cgs, Rd, Rs, Cgd, parasitic capacitance, planar transistors, Dey, parasitic extraction, gate input capacitance, fin profile, FinFET extraction, Dillinger, resistance
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GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
By Richard Goering
on April 29, 2013
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture...
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Filed under: lithography, advanced node, Double Patterning, OPC, GlobalFoundries, CDNlive, Cadence, FinFET, CDN Live, SADP, RET, 10nm, LELE, LFLE, Jongwook Kye, DTCO, Kye, design technology co-optimization, multiple patterning
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Cadence DAC 2013 and Denali Party Update
By Richard Goering
on April 25, 2013
A very special Design Automation Conference (DAC) will take place in early June - it's the 50 th anniversary of this conference, which has long been a focal point of the EDA industry. This year Cadence is celebrating its 25 th anniversary and has...
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Filed under: Industry Insights, DAC, Denali Party, Design Automation Conference, Austin, Cadence at DAC, DAC 2013, DAC microsite, Cadence Theater
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