Challenging Misconceptions About Verification Languages
By Richard Goering
on March 10, 2010
One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way...
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Filed under: Industry Insights, DVCon, SystemC, OVM, verification, e, OOP, HVL
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Q&A: New Challenges, New Solutions In IC Implementation
By Richard Goering
on March 8, 2010
Advanced nodes are raising tough new challenges for analog/mixed-signal and digital IC implementation, according to David Desharnais, group director and product manager for implementation at Cadence. In this interview, he notes where IC designers are...
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Filed under: Industry Insights, DFM, Encounter, CPF, SoC, digital implementation
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DVCon OVM Panelists: Easing The Debug Challenge
By Richard Goering
on March 4, 2010
The good news about the Open Verification Methodology ( OVM ) and the advanced verification techniques it supports is that verification engineers are now finding more bugs than ever. The bad news is that the bottleneck is shifting to debugging. What are...
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Filed under: Industry Insights, DVCon, specman, OVM, verification, Debug
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DVCon Panel: Three Ways To Minimize Verification Effort
By Richard Goering
on March 2, 2010
With verification taking up more and more of the design cycle, is there any hope that verification will keep up with escalating design complexity? Yes, according to panelists at the DVCon conference Thursday Feb. 25. From the discussion, I distilled three...
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Filed under: DVCon, SystemC, TLM, verification, Industsry Insights, MDV
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DVCon Panel: Why Verification Engineers Are “Sleepless”
By Richard Goering
on March 1, 2010
I view a panel as successful when I leave the room knowing more than when I came in. Such was the case at the "What keeps you up at night" panel at DVCon Feb. 24, which offered some interesting, provocative, and in several cases surprising perspectives...
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Filed under: Industry Insights, DVCon, OVM, verification, IC Design, VMM
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Lip-Bu Tan Keynote: Rethinking EDA For 2010 And Beyond
By Richard Goering
on February 25, 2010
Business conditions are looking up for the EDA and semiconductor industries, but customer concerns have shifted, according to Lip-Bu Tan, president and CEO of Cadence. At a DVCon keynote speech Feb. 24, Lip-Bu described a new landscape in which EDA providers...
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Filed under: EDA, Industry Insights, DVCon, TLM, Lip-Bu Tan
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DVCon SystemC Day Quandry: Need for Third Party TLM IP
By Richard Goering
on February 24, 2010
Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was...
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Filed under: Industry Insights, DVCon, SystemC, ITRS, C-to-Silicon, NASCUG, OCP, TLM IP
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DVCon SystemC Day – Forging A TLM Design/Verification Flow
By Richard Goering
on February 23, 2010
Advanced design technologies are of no value unless there's a coherent, workable methodology that supports them. SystemC transaction-level modeling (TLM) has lacked a methodology that goes all the way to silicon without major gaps. Independent verification...
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Filed under: Industry Insights, DVCon, SystemC, OSCI, TLM, verification, NASCUG
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EDAC CEO Forecast Panel: Takeaways For 2010 And Beyond
By Richard Goering
on February 19, 2010
After a hard year and a half for the EDA industry and the economy in general, what's on tap for 2010 and beyond? The EDA Consortium's annual "CEO Forecast and Industry Vision" panel Feb. 18 had what I would call a "cautiously upbeat"...
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Filed under: EDA, EDAC, Industsry Insights, CEO Panel, EDA Consortium
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Q&A: How System Design And Verification Can Go “Mainstream”
By Richard Goering
on February 18, 2010
System design and verification are part of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this...
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Filed under: Industry Insights, DVCon, FPGA, TLM, RTL Compiler, System Design an Verification, OVM, System C, C-to-Silicon, Incisive, IEX
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