Home > Community > Blogs > Industry Insights > archived webinar an introduction to high level synthesis hls
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Archived Webinar – An Introduction to High-Level Synthesis (HLS)

Comments(0)Filed under: HLS, webinar, Cadence, high level synthesis, Forte, Pursley, behavioral synthesis

High-level synthesis (HLS) is rapidly entering the IC design mainstream - but how much do you know about this emerging technology? A recently archived Cadence webinar sets the record straight about what HLS is (and is not), how it works, who's using it and why, what advantages users are seeing, and what's available from an IP standpoint.

The webinar was titled "Tapping into High-Level Synthesis for Improved Time to Market, Quality of Results, and IP Reuse." It was presented by David Pursley, senior product manager at Cadence, and was based on a Cadence presentation given at the recent Design Automation Conference.

You probably know that SystemC-based HLS can greatly accelerate productivity and time to market. That's because it works at a much higher level of abstraction than RTL coding and synthesis. What you may not know is that users are seeing up to 20% better quality of results (power, performance, area) and 5-10X faster verification. And for some, the biggest advantage of all is the ability to quickly retarget and reuse high-level IP blocks while generating a variety of potential micro-architectures.

HLS Reaches Out

Pursley started the webinar by noting that the Cadence purchase of Forte Design Systems is the "biggest news" for HLS thus far in 2014. The Forte Cynthesizer HLS tool, he said, is known for its strong quality of results for datapath-centric designs, world-class arithmetic IP, and valuable SystemC and IP development tools. The Cadence C-to-Silicon Compiler uniquely offers fine-grained control over quality of results, extensive visualization capabilities, and incremental synthesis ECO support. Between Forte and Cadence, 15 of the top 20 semiconductor companies use HLS, and there have been over 800 IC tapeouts.

Pursley noted that HLS has long been known for datapath-centric applications such as video, DSP, and image processing. In recent years, however, HLS has been used for more and more control-centric applications, such as Ethernet controllers, micro-controllers, and memory interface control.

So what exactly is HLS? "At a very fundamental level, HLS takes abstract descriptions and adds whatever detail is needed to produce RTL," Pursley said. As shown in the diagram below, HLS takes in SystemC and C++ synthesizable behavior models, creates the finite state machines (FSMs) and datapaths, and generates Verilog RTL that you can put into your existing HLS flow. Constraints and directives provide guidance to the HLS tool, and make it possible to quickly generate many different micro-architectures.

According to Pursley, benefits of HLS may include:

  • 10X better productivity and IP reuse. The technology separates functionality from implementation, and provides re-targetable high-level IP.
  • 5X faster and better verification. This is due to the use of fast transaction-level modeling (TLM) and a consistent verification platform.
  • 20% better quality of results (QoR) for power, area, and performance.

Wait a minute, you may be asking - how can automatically generated RTL code provide better QoR than hand-coded RTL Verilog? Pursley cited two reasons. One is that the HLS tool can do a better job of looking over the entire design to provide the best ways to share resources. Another reason is that you can quickly generate many RTL designs, and pick the best one. Pursley showed a customer example in which the synthesized code had a 0.8X area improvement over the handcrafted code, while taking just 2.9 weeks compared to 6 weeks for handcrafted RTL.

As shown below, HLS allows the designer to focus on functionality, architecture, and constraints. There is no need to break logic down into clock cycles, manually create the FSM, or provide explicit memory or register management.

Pursley cautioned, however, that writing SystemC code is not the same as writing embedded software. The implementation is very different and the cost tradeoffs are different. For example, if you think about an imaging pipeline, it is commonplace for the software to operate on frames of data at any given time. In the hardware world that would be extremely expensive.

But using HLS is not the same as writing RTL, Pursley observed. In the presentation, he showed how the SystemC language standard provides a high level of abstraction along with the necessary hardware constructs.

The IP Edge

In the first generation of design, Pursley said, you may notice a 5-10X turnaround time improvement by using HLS. But the real "win" comes after that, when you start re-targeting and reusing high-level IP. Perhaps you need to move to a new technology node, a faster clock speed, an additional power reduction - "no matter what, you can come back to this [IP] code and generate any one of those variants just by changing the constraints," he said.

The webinar also discussed the benefits of HLS for verification and the ability to reuse testbenches across different levels of abstraction. You start with very high-level TLM models and then substitute pin-level interfaces for the TLM interface. Finally you reuse the same testbench for RTL verification.

Pursely provided a quick tour of Cadence synthesizable IP. One of the more popular selections is a line buffer. Here, users develop an algorithm and define a working set, and the IP handles all the implementation details. Cadence also provides IP for external memories and clock domain crossing interfaces.

The webinar showed how C-to-Silicon Compiler handles ECOs with incremental synthesis. It also showed how HLS supports low-power design techniques such as clock gating and FSM optimization. In a number of instances the webinar cited specific case studies with customers and quantified the benefits they achieved.

To view the webinar, click here. A Cadence log-in is required - quick and easy registration if you don't have one.

Related Blog Posts

Sean Dart Q&A: Former Forte CEO Discusses Past, Present and Future of High-Level Synthesis

How Cadence Acquisition of Forte Boosts High-Level Synthesis

DAC 2014: High-Level Synthesis (HLS) Users Share Advantages, Challenges

 

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.