Home > Community > Blogs > Industry Insights > dac 2014 panel finfet ic design poses no roadblocks but lots of details
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DAC 2014 Panel: FinFET IC Design Poses No Roadblocks, but Lots of Details

Comments(0)Filed under: IC Design, 20nm, custom/analog, FinFET, DAC panel, 16nm, 14 nm, DAC 2014

FinFET transistors promise enormous power and performance advantages at process nodes below 20nm, but how will they impact IC design? If you're a digital designer, not much changes - but if you're a custom/analog designer, there's a lot to learn, according to panelists at the recent Design Automation Conference (DAC 2014) in San Francisco.

Titled "FinFET and IC Design: Mountain or Mole HIll?", the panel was moderated by Jamil Kawa of Synopsys, and it featured these panelists (listed in the order of their opening presentations):

  • Richard Rouse, principal technologist, Microsoft
  • Hugh McIntyre, principal member of technical staff, AMD
  • Jean-Marie Brunet, product marketing director, Mentor Graphics
  • Wilbur Luo, senior group director for custom IC and simulation, Cadence

Kawa opened the panel by noting that Intel's 22nm "tri-gate" (FinFET) announcement three years ago opened the floodgates for FinFET technology development at 16nm and 14nm. Semiconductor companies are looking to FinFETs as a way of continuing the scaling promised by Moore's Law. "Has design with FinFETs been disruptive, or is it business as usual?" he asked the panelists. Here are some of their responses.

Rouse - Familiar for digital, challenging for analog

Rouse said that Microsoft sees FinFETs as a way to provide lower power, continue Vdd scaling, reduce costs, build quieter products (no fans needed for cooling), and prolong battery life. "From a systems perspective, we are very bullish on this technology," he said.

Digital placement and routing tools must handle FinFET grids, but for the most part they do this pretty well, Rouse said. "For the digital designer, FinFET doesn't look that different from 20nm. [Double patterning] coloring comes into play, but if you're familiar with 20nm it's the same sort of thing."

Custom/analog designers, however, have a much steeper learning curve. Working with bandgap references, bipolar junction transistors, guard rings, and diodes is challenging. There are new constraints and rules about lining up fins. Given more Rs (resistances) and Cs (capacitances), circuit simulation time may be two times longer. And metal fill places extra constraints on analog geometries, particularly resistors and capacitors. "In general, the analog tool chain is significantly changed," Rouse said.

McIntyre - "No fundamental roadblocks, but lots of details"

Digital designers won't see much difference with FinFETs, McIntyre said. In many respects, he noted, the move from 28nm to 20nm was a more difficult transition than the move from 20nm planar transistors to FinFETs. To move to 20nm, designers had to cope with double patterning, local interconnect, and more complex design rules.

However, FinFETs pose some complications and difficulties for digital design. "The main thing is that you definitely find higher gate capacitance and source-drain resistance," McIntyre said. Further, designers need to plan the placement of standard cells and macros in accordance with the fin grid. "Miss a design rule by 5nm, and the whole fin could be lost," he noted.

McIntyre also brought up the often-discussed topic of "width quantization," which comes about because standard cell designers can no longer use arbitrary transistor widths but must instead use an integer value of fins (you can't have 2.5 fins). CAD tools, he noted, need to "switch mindset" to think in terms of the number of fins rather than device width. This means new versions of tools will be needed.

Brunet - Changes needed to EDA tools

Brunet listed several challenges that FinFETs pose for the CAD ecosystem, including the following points.

  • A new circuit simulation capability is needed. FinFET models are much more complex to simulate, causing long runtimes.
  • Placement and routing requires a fin grid, and everything must be roughly aligned to it.
  • FinFET verification requires some fin-specific rule checking.
  • Extraction is a "big challenge" for FinFETs. First, you need to be able to extract correct fin parasitics. Secondly, there are far more Rs and Cs to extract.

Brunet concluded with some questions that still need answers. How do you do analog design with quantized features? How do you compensate for the lack of body biasing? How do you design with a black box in the layout? "Design teams need to rely less on experience and more on simulation," he said.

Luo - New custom/analog design flow is needed

Luo identified "three big issues" related to FinFET design. First, the 3D geometry of FinFETs results in 5X-10X more Rs and Cs than planar transistors, and gate capacitance is large. This leads to longer extraction and simulation times. Secondly, variability and reliability are impacted by stress and proximity effects, process variations, electromigration, and other causes, and this in turn affects circuit performance. Third, layouts require fin grids, discrete device widths, and dummy gates, making automation necessary to stay productive.

Luo said that custom/analog flows need to get an early view of the impact of layout on the design. "Instead of just doing circuit design in isolation, you want to get a quick prototype layout so you can back annotate all those layout-dependent effects into your simulation," he said. Also, in-design verification is important so designers can continuously verify rather than wait until the very end. And "smart" RC extraction must take multi-patterning into account.

The following diagram in Luo's presentation shows requirements for a FinFET-aware, advanced node custom/analog flow:

And what about digital design? "The big change from the digital side is making sure you're on the right grid and that the grids match up through the hierarchy," he said. "Make sure double patterning is clean as you place things. Make sure the routing is gridded and correct by construction. Physical verification is pretty much the same."

Q: Can you comment on the learning curve for FinFET design?

McIntyre: "It's a long, slow, rumbling learning curve." That curve starts with establishing feasibility and working out the basic rules. Then come standard cell libraries, custom layouts, and test chips, and analyzing the results of these.

Luo: Going to 20nm is a "much bigger jump" than going to FinFETs.

Q: How many fins do we need in a device to have a good digital design?

McIntyre: Some of the foundries have found that a single fin really doesn't work very well. It doesn't provide good performance or easy verification. Once you get past two fins, designs with three fins and four fins can work well.

Brunet: It also depends on the drive strength you're trying to get to.

McIntyre: Fin quantization costs perhaps 5% of the area because you lose some of the device width you could have had. If the layout would allow 3 ½ fins, you only have 3. With two fins you can reduce the penalty.

Q: What's the impact of FinFETs on library characterization?

Brunet: "From a characterization perspective, what's different is the layout. Everything is on a grid. I think library characterization is very different."

Q: Can you comment further on the interactive nature of layout and simulation for analog designs?

Luo: In addition to an early view of layout, you need a whole flow that is tied together and that has real-time parasitics and electromigration analysis. Otherwise convergence will be difficult. "Ideally, you have an early view of layout instead of waiting for layout engineers to finish their layout, feed it back, and then find a problem."

Richard Goering

Related Blog Posts

EDPS Workshop - a Review of FinFET Parasitic Extraction Challenges

2014 TSMC Technology Symposium: Full Speed Ahead for 16nm FinFET Plus, 10nm, and 7nm

BSIM-CMG FinFET Model - How Academia and Industry Empowered the Next Transistor

 

 

 

 

 

 

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.