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DAC 2014 Cadence Theater – Customers, Partners Outline Challenges and Successes

Comments(0)Filed under: DAC, Design Automation Conference, Cadence Theater, DAC 2014, Cadence DAC Theater

One of the best things about the Design Automation Conference (DAC 2014) is the ability to hear how other engineers are solving tough IC and system design and verification challenges. And the best place to do that is the Cadence Theater, located at the Cadence booth (#2616). The Theater will host half-hour customer and partner presentations from 9:30 am Monday, June 2, to 3:30 pm Wednesday June 4.

Over 40 presentations are currently scheduled. They are open to all DAC attendees and no reservations are required. Companies that will be presenting in the Cadence Theater include AMD, ARM, Altera, Broadcom, Cisco, CSR, Fujitsu, GLOBALFOUNDRIES, National Instruments, Qualcomm, Samsung, Solarflare, TSMC, Tektronix, TowerJazz, and Xilinx. 

Similar presentations were offered at the Cadence DAC Theater in 2012 and 2013, and many attracted standing-room-only crowds. These informal presentations are given in an interactive setting with an opportunity for questions and answers. Audio recordings with slides will be available at the Cadence website after DAC. To access recordings of the 2013 DAC Theater presentations, click here.

This Cadence DAC Theater presentation drew a standing-room-only crowd in 2013

A complete, updated listing of the theater presentations is available here. Rather than duplicate the list, I've identified several key categories and listed some of the relevant presentations.

HW/SW Co-Development - Emulation, Prototyping

  • Monday, 1:30 pm - NVIDIA, Palladium for Android SW Validation, GPU Testing on ARM v8 SoC
  • Monday, 3:00 pm - Xilinx, Industry-Leading Solutions for FPGA-Based Prototyping
  • Monday, 4:00 pm - AMD, Application-Level Power Event Monitoring with Hybrid Emulation
  • Wednesday, 12:00 pm - Dini Group, Hardware Solutions for FPGA-Based Prototyping
  • Tuesday, 1:00 pm - Solarflare, Emulating a Dual-Port 10G/40G NIC on Palladium and RPP
  • Tuesday, 2:00 pm - ARM, Accelerating Graphics Software Simulation in Virtual Platforms
  • Tuesday, 3:00 pm - Samsung and Cadence, Validate Complex Multi-Core Designs, Optimize HW/SW Performance
  • Wednesday, 1:30 pm - CSR, Using Palladium/VSP Hybrid to Accelerate SW Development

Signoff

  • Monday, 12:00 pm - TowerJazz, Using Cadence PVS for Signoff at TowerJazz
  • Monday, 3:30 pm - Marvell, Fast and Accurate Extraction for Advanced Nodes
  • Tuesday, 4:30 pm - Tektronix, System Signal Integrity Expands into the Lab
  • Tuesday, 11:30 am - Samsung, Enabling Cadence Signoff Technologies for 14nm FinFET
  • Wednesday, 3:00 pm - X-FAB, Enhanced Black Box Design Flow Using Cadence PVS

Custom/Analog and Mixed Signal

  • Monday, 9:30 am - STMicroelectronics, Cadence In-Design VIPVS and LDE Adoption in STM SmartPower PDK
  • Tuesday, 10:00 am - TowerJazz, Analog/MS Flow with EAD, Device Checker, and PVS PERC Features
  • Tuesday, 10:30 am - Samsung, 14nm FinFET Design Using Virtuoso Advanced Features
  • Tuesday, 4:30 pm - STMicroelectronics, Virtuoso Mixed-Signal "Smart Power" Implementation Flow

Verification

  • Monday, 12:30 pm - National Instruments, Post and Pre-Silicon Verification - The Best of Both Worlds
  • Tuesday, 9:30 am - Juniper, Incremental Elaboration in the Verification Flow
  • Wednesday, 11:00 am - Cadence, AMD, Broadcom, NVIDIA - Accelerated VIP, a Deep Dive Based on Customer Case Studies

Digital Implementation/Synthesis

  • Monday, 2:30 pm - Netspeed, Bringing the Power of Synthesis to SoC Design
  • Monday, 5:00 pm - Broadcom, SoC Static Power Verification with Encounter Conformal Low Power
  • Tuesday, 3:30 pm - Fujitsu, Physical RTL Synthesis Improves Timing and Congestion
  • Wednesday, 12:30 pm - Qualcomm, SoC Implementation Experience Using RC-P/Conformal ECO/CCopt
  • Wednesday, 2:30 pm - Cisco, Physical RTL Synthesis Strategies on Networking ASICs

Other Cadence Theater Presentations

  • Monday, 2:00 pm - Broadcom, Optimized Layout-Aware Scan with Third-Party DFT
  • Tuesday, 11:00 am - IBM, Overcoming Pattern-Induced Place-and-Route Challenges at 10nm
  • Tuesday, 11:30 am - CoFluent, Top-Down Design Methodology with CoFluent Studio and HLS
  • Tuesday, 12:30 pm - Methodics, IP and Design Data Management for SoC Designs
  • Wednesday, 10:30 am - Altera, Flip-Chip Co-Design Planning Using Cadence OrbitIO

Every hour on the hour, there will be a giveaway for a set of Bose noise-cancelling headphones, a Kindle, or a GoPro Hero3 video camera. See the Cadence Theater schedule for details.

Join us for a special event at the Cadence Theater Wednesday at 3:30 pm, when the Cadence Academic Network will hold a PhD Forum Award ceremony.

See you at DAC 2014! And be sure to view our Multimedia Site for live blogging and photos and videos from DAC. For a complete overview of Cadence activities at DAC, see our DAC microsite.

Richard Goering

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