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DDR4 in 16nm FinFET: Future-Proof Your SoC Design

Comments(0)Filed under: TSMC, Cadence, DDR4, PHY IP, FinFET, 16nm, DDR4 PHY

Cadence this week (May 19, 2014) is announcing the first DDR4 PHY IP built on TSMC's 16nm FinFET process. The 3200Mbps DRAMs that can take best advantage of this capability aren't shipping in volume yet - but you can "future-proof" your 16nm SoC design by using a DDR4 controller and PHY that can scale up to 3200Mbps as the parts become available. Further, the availability of 16nm FinFET support for very high-speed memory might provide yet another incentive for considering that process node.

DRAMs today are available at 2133Mbps, a speed supported by both the DDR3 and DDR4 standards. You can easily get this performance in a 28nm process. (Cadence, in fact, announced in January that its DDR4 PHY IP achieves 2667Mbps in 28nm). But according to Kishore Kasamsetty, product marketing director at Cadence, you really need to go to a FinFET process to get 3200Mbps performance.

And who needs that performance? The first adopters will probably be enterprise applications such as servers, network switching, and storage fabrics. These applications can also take advantage of the overall power, performance, and area advantages of a sub-20nm process.

"We don't know exactly when DRAMs rated higher than 2400Mbps will go into high volume, but if you're designing today on an advanced process using IP optimized to take advantage of the higher performance offered by the FinFET process, you are set for the future" with the Cadence DDR4 PHY, Kasamsetty said.

As he pointed out, you don't want to have to redesign your DDR4 PHY interface when the new parts come out. Even if your application needs only a maximum of 2400Mbps performance today, the Cadence PHY IP that's capable of 3200Mbps operation will provide additional robustness and improved system margins. As the application needs increase, and higher speed DRAMs are available, designers can reuse the same DDR PHY IP without having to do a costly redesign or procure new IP.

A Long Time Coming

Although JEDEC began work on a successor to DDR3 around 2005, the JEDEC DDR4 standard was not published until September 2012. Compared to DDR3, DDR4 offers higher performance, greater reliability, reduced power, higher capacity, a more robust RAS (reliability, availability, and serviceability) feature, and better die stacking capabilities. DDR4 potentially provides 50% more bandwidth and 20% less power than DDR3.

The JEDEC web site cites the following DDR4 features:

  • Per-pin data rate of 1.6 giga transfers/second, scalable to 3.2 giga transfers/second (3200Mbps)
  • A pseudo open drain interface on the DQ bus
  • Geardown mode for 2,667 MT/s and beyond
  • 8n prefetch architecture with two or four selectable bank groups, permitting DRAMs to have separate activation, read, write, or refresh operations in each bank group
  • Three data width offerings - x4, x8, and x16
  • DBI (Data Bus Inversion), which reduces power consumption and improves data signal integrity
  • Programmable refresh, which reduces performance penalty of dense DRR4 devices
  • Stacks of up to 8 memory devices present only a single signal load

For a deep dive into DDR4, you can purchase presentations from the February 2013 JEDEC DD4 workshops.

Not all PHY IP is created equal. The Cadence DDR4 PHY IP works with Cadence DDR4 controller IP, which is a soft IP block. The controller has, however, been updated with pipeline and speed improvements to support scaling up to 3200Mbps. Here are some key features of the 16nm-enabled Cadence DDR4 PHY:

  • Supports an unbuffered DIMM (UDIMM) and registered DIMM (RDIMM) with RAS features such as cyclic redundancy check (CRC) and DBI
  • Uses 4X clocking to minimize duty cycle distortion (internal clock edge is twice as steep as that required by the external system)
  • Multi-band power isolation increases noise immunity (analog circuits are isolated from jitter-sensitive digital circuits)
  • I/O with slew rate control makes higher data rates possible
  • IP is developed to support customer metal stack options

Both the Cadence DDR4 controller and PHY have been verified in silicon from TSMC's 16nm FinFET process. Previous to the 16nm FinFET support, the Cadence DDR PHY IP has had a 10-year history of use (originally with Denali Software) and has been extensively validated with multiple hardware platforms.

A Video Overview of DDR4

In a recent Whiteboard Wednesdays blog post, Kishore Kasamsetty provides a history of DDR4 technology, and reviews the power and bandwidth improvements of DDR4 over DDR3. He also discusses the memory standard's specifications and the engineering challenges of meeting those specifications. Finally, he presents requirements for the DDR4 controller and PHY.

A datasheet for the 16nm-enabled DDR4 PHY is located here.

Richard Goering

 

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