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DAC 2014: Semiconductor IP Trends Revealed at “IP Talks!”

Comments(1)Filed under: IP, ChipEstimate.com, semiconductor IP, IP Talks, DAC 2014

Want to know more about the design and verification IP that makes advanced system-on-chip (SoC) design possible? There's no better place than IP Talks!, a series of ongoing presentations at the ChipEstimate.com booth (#1533) at the Design Automation Conference 2014 (DAC 2014), set for June 2-5 in San Francisco, California.

Now going into its 8th year, IP Talks! includes over 30 half-hour presentations from the world's leading IP providers and foundries. The talks run continuously from 10:00am to 5:00pm Monday, Tuesday, and Wednesday June 2-4. Held in an informal setting, the talks address the challenges faced by SoC design teams, and show how the latest developments in semiconductor IP can contribute to design success.

IP Talks! takes place in an informal setting at the ChipEstimate.com booth

This year's keynote IP Talks! presentation will be given at 10:30am Monday by Peter McGuiness, director of multimedia technology marketing at Imagination Technologies. The presentation topic is "Visuals to Vision: The Changing Role of the Image Sensor." Other IP providers giving talks include ADICSYS, Argon Design, ARM, Cadence, eSilicon, Ferric Semiconductor, Methodics, Mixel, Open-Silicon, Sidense, SilabTech, Synopsys, True Circuits, and Uniquify.

You can learn more about Cadence design IP at 2:30pm Monday or 2:00pm Wednesday, and about Cadence verification IP (VIP) at 4:30pm Tuesday. One more incentive - if you come to the 11:30am or 3:30pm presentations on any of the three days, you have a chance to win a Bose Noise Cancelling Headphone or an HP Chromebook. There's also a free cocktail event, sponsored by True Circuits, at 5:00pm Monday.

To see the latest schedule for IP Talks!, click here. Presentations from IP Talks! 2013 are available here (scroll to bottom of the schedule).

Richard Goering

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By GLENN FORSLIN on May 28, 2014
Does this show, or Cadence for that matter, offer any design to test conversion tools? We make a nice eVCD to STIL conversion toolset. I would think that Cadence and others at DAC would offer conversion to get patterns to the tes system.Thanks, Glenn

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