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IEEE Panel Charts “Top SoC Design Challenges”

Comments(0)Filed under: virtual platforms, cloud computing, EDPS, SoC design, IEEE panel, FD-SOI, IEEE CS SCV

What are the top ten challenges in system-on-chip (SoC) design today? Can virtual platforms, cloud computing, and fully depleted silicon-on-insulator (FD-SOI) be part of the solution? Experts discussed these points April 8, 2014, in a panel organized by the IEEE Computer Society of Silicon Valley (IEEE CS SV) and held at Cadence headquarters in San Jose, California.

This "Top SoC Design Challenges" panel discussion served as a kind of preview for the Electronic Design Process Symposium (EDPS 2014) scheduled for April 17-18 in Monterey, California, where the above issues will be discussed in much more depth. Additionally, three of the four panelists listed below (McLellan, Sehgal, Swan) will be speakers at EDPS 2014.

Panelists were as follows, as shown left to right in the composite photo below. Moderator Hans Spanjaart, senior program manager at Altera, is in the rightmost position.

  • Tom Dillinger, CAD Technology, Oracle
  • Paul McLellan, Blogger, Semiwiki.com
  • Naresh Sehgal, SW Director for FPGA Based Silicon Platforms, Intel
  • John Swan, SoC Technologist, Swan on Chips

Go Back and Shift Left

Swan opened the panel by admonishing listeners to "go backward in the [design] flow and shift left." This means that software development and hardware/software co-verification need to take place much earlier than they typically do today. Swan noted that software development lags hardware development in today's flows. Architects perform hardware/software partitioning without much exploration of architectural tradeoffs. They then pass the design to hardware development teams, who jump right into RTL coding.

Virtual platforms can make a big difference. By combining fast processor models with transaction-level peripheral models and legacy IP, Swan noted, virtual platforms can provide software development, hardware validation, and hardware/software integration. Bringing virtual platforms into the flow also allows more architectural exploration.

Why has the development of electronic system level (ESL) flows been slow? Swan cited several reasons - insufficient model availability, lack of expertise that encompasses both hardware and software, and (typically) no path to implementation through virtual platforms. Larger companies find it easier to adopt ESL flows because they have the manpower.

Sehgal noted that new SoCs are costing upwards of $300 million, and suggested several ways to reduce costs, including derivative designs, IP reuse, and a "shift left" to develop and verify software earlier. Cloud computing is another option. Today, he noted, there aren't many EDA tools in the cloud, and chip design companies are concerned about protecting their IP. Overcoming these barriers will lower the cost of design, Sehgal said.

While most of the semiconductor industry is assuming that FinFET transistors will prevail below 20nm, there is in fact another option, according to McLellan. That option is FD-SOI, a technology championed by ST Microelectronics. Basically, an FD-SOI transistor has a very thin channel with an insulator behind it. While FinFETs will be very expensive to manufacture, FD-SOI may be even less expensive than today's planar transistor processes, he said.

Swan, Sehgal, and McLellan will all speak in more depth about these topics at EDPS.

The Top Ten SoC Challenges - A Designer View

With apologies to the retiring David Letterman, Tom Dillinger provided a "top ten" list of challenges for SoC design, counting backwards down to the biggest challenge. Here's the list.

  • 10 -- IP Quality, Complexities of IP Integration. We are increasingly dependent on IP that comes from a number of sources. Functional models and electrical models must be accurate. Standards activities such as IP-XACT are critical.
  • 9 - SoC Testability. The complexity of the IP we're adding, and the demand to test that IP in isolation, add to the complexity of developing a comprehensive test set.
  • 8 - RC Delay Management and Optimization. This might also be called "managing your metal set." Foundries are providing a lot of options, but picking the right metal stack remains challenging.
  • 7 - Power Optimization. Everybody worries about power management and optimization. Power format description standards can help.
  • 6 - Hierarchical Data Management. As the complexity of IC designs grows, the volumes of data that we're managing and the number of versions, corners, and power domains all grow exponentially.
  • 5 - Functional Verification. "If anybody can answer the question of how much verification is enough, come and see me after the panel and we'll make a lot of money."
  • 4 - Variation-Aware Analysis. As process nodes shrink, there are more sources of process variation that need to be managed. If you're transitioning to FinFETs there are additional sources of variation.
  • 3 - DFY and DFM. Design for Yield (DFY) is critical because we're all interested in making money. Without Design for Manufacturing (DFM) we won't have manufacturable parts we can sell.
  • 2 - Electromigration (EM). In the future, more designs will be EM-limited. We will have to dust off our thermal heat flow equations.
  • 1 - Lithography Dependencies. The chip designer can no longer throw a design over the wall to a mask designer, wait for it to come back, review the layout, and complete the implementation. Today's processes have layout-dependent effects that you need to understand from the very start. Also, double patterning lithography - the norm at 20nm - has a massive influence on everything from your cell design to your cell integration.

To view an on-demand webcast of this panel discussion, click here. Microsoft Silverlight is required.

Richard Goering

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Electronic Design Process Symposium (EDPS) Reviews Design Flow Challenges and Solutions



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