Since its initial release as an Accellera standard three years ago, the Universal Verification Methodology (UVM) has become one of the most successful and widely used EDA standards. In addition to its original goal of verification IP (VIP) interoperability, UVM has popularized such concepts as stimulus generation based on sequences, communication based on transaction-level modeling, test execution using runtime phases, and a register layer.
The DVCon 2014 conference offered a March 3 tutorial titled "UVM - What's Now and What's Next." What's next is the pending UVM 1.2 release, which is expected to become the official version of UVM in the very near future. Uwe Simm, solutions architect at Cadence and a member of the Accellera UVM Working Group, has been involved in the development of UVM 1.2 and was a speaker at the tutorial.
The day after the tutorial, I caught up with Uwe Simm for a short video interview. He noted that the new release is "an evolution rather than a revolution." We discussed messaging improvements that allow object-oriented features, improvements that make phasing more usable, and a sequence library that is now part of the official UVM standard.
If the video icon below does not open, you can view the video here.
To learn more about UVM and the UVM 1.2 release, see the Accellera UVM community web site at http://www.accellera.org/community/uvm/. You can download a user guide and reference implementation at http://www.accellera.org/downloads/standards/uvm.
Other DVCon 2014 Cadence Blog Posts
DVCon 2014 Panel: Did We Create the Functional Verification Gap?
Jim Hogan at DVCon 2014: Functional Verification Faces "Abundant Chaos" from New Technologies
DVCon 2014 in Review: Formal Verification, Value Chain, and the Industry's Future
Lip-Bu Tan at DVCon 2014: EDA/Silicon Ecosystem Crucial to Innovation