Much has been written (some by me) about the challenges of timing closure for IC designers. It turns out that timing closure is increasingly a problem for PCB designers as well. The Cadence Allegro TimingVision environment, announced today (March 5, 2014), is an innovative solution that combines an embedded timing engine, color-coded real-time visual feedback (shown at right), and auto-interactive technologies for delay and phase tuning.
PCB designers, like IC designers, are under increasing pressure to rapidly turn out products that are faster, have more bandwidth, and use less power. This pressure is leading to the increased use of high-speed standard interfaces, like DDR3 or DDR4. Timing relationships for these interfaces are complex, with complicated matching requirements. Tuning signals for these interfaces is a frustrating and time-consuming project.
Meanwhile, supply voltages have decreased from 1.8V to 1.5V and 1.2V. In consequence, signals are very sensitive to ripples in the power supply. A ripple that was tolerable at 1.8V may not be tolerable at 1.2V. Finally, signals are closer together because form factors are smaller, increasing the odds of crosstalk.
Constraints are getting more complex because of sensitivity, and because higher speed signals require tighter tolerances and tighter margins. "That translates into a complex set of electrical and layout implementation constraints," observed Hemant Shah, product marketing group director at Cadence.
Thrashing Back and Forth
Interdependencies between signals are a major challenge, according to Shah. "A change in one signal in one group will cause a problem in other groups," he said. "PCB designers have to plan tuning as well as routing, and pick the right set of signals to tune first. Otherwise they will be thrashing back and forth. They'll fix one signal, find a problem with another one, fix the other one and then have a problem in the first one. This is a trial and error process with current technology."
PCB designers can get some help from the Allegro Constraint Manager, which shows whether signals are in compliance with constraints (green for yes, red for no). However, designers have to go back and forth between the design canvas and Constraint Manager, which does not provide physical information. Feedback is provided on a matched group level, and all signals have to meet timing for the group to go "green." Interdependencies and margins between groups are calculated by the designer manually.
Providing a new level of support for PCB timing closure, the Allegro TimingVision environment includes these three components:
- An Embedded Timing Engine analyzes signal interdependencies to develop "smart" delay and phase targets. This helps designers develop strategies to address timing closure issues.
- Real-time visual feedback is provided on the design canvas. Color coded timing and phase information appears in real time—green is good, red is short, and yellow is long. This eliminates going back and forth between the design canvas and the Constraint Manager. Also, designers can see the dependencies of signals on one another.
- Auto-interactive technologies include auto-interactive delay tuning (AiDT) and auto-interactive phase tuning (AiPT). AiDT allows designers to quickly tune a selected set of signals, such as a byte lane or even an interface. It was previously available as a standalone utility, and now it is fully integrated with TimingVision. AiPT is new with TimingVision.
The illustration below shows how AiPT can help designers to meet differential pair phase requirements. AiPT offers both static and dynamic phase compensation. Once nets are selected, a variety of user-driven compensation techniques can be deployed.
TimingVision offers a DRC Timing Mode, Smart Timing Mode, and Smart Phase Mode. DRC Timing Mode ensures compliance as a design nears completion. Smart Timing Mode identifies critical signals and defines timing closure goals for the user with real-time feedback. Smart Phase Mode identifies exact sections of differential signals that require tuning to meet phase skew goals.
In the illustration at the top right, red indicates the target mode, and the bottom-most yellow signal is the longest signal. Working in DRC mode, the designer will try to match the other signals to the longest signal. Signals will not go green until they are within tolerance of all other signals in the match group.
In the Smart Timing Mode depicted at the lower right, the embedded timing engine identifies a new target signal (formerly the bottom-most yellow signal). The timing engine calculates new min/max "goals" based on the signals in the interface. Signals go green as each one meets the independent min/max goal.
While not a requirement, TimingVision can be coupled with Sigrity power-aware signal integrity analysis software. "This really ensures that your interfaces are in spec," Shah said. TimingVision plus Sigrity lets users model simultaneous switching noise, perform signal and power integrity simulations, predict bit error rate, enable power integrity signoff, and run package and model extraction for system-level analysis. Shah noted that the TimingVision environment can be used for IC package design as well as PCB design.
In a success story at Cadence.com, Taiwanese computer manufacturer Pegatron used the AiDT feature in Allegro PCB Designer. The company reported up to a 67% faster routing process and a 75% reduction in engineering resources required for routing and tuning.
TimingVision is available now as part of the Allegro PCB Designer High-Speed Option. A landing page with further information is available at Cadence.com.