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Archived Webinar: Dynamic Power Analysis and Low-Power Verification with Emulation

Comments(0)Filed under: Palladium, emulation, Palladium XP, low power verification, dynamic power analysis, DPA

Nearly every IC design these days is a low-power design—and fast and accurate power analysis is needed from the system level on down. In a newly archived two-part Cadence webinar, one speaker explains why and how to use dynamic power analysis with emulation, while another speaker shows how low-power verification can be used with the Cadence Palladium XP emulator (right).

The webinar was presented Dec. 11, 2013, by Dieter Thuemmel, solutions architect at Cadence, and Joel Ake, staff product engineer at Cadence. You can access the archived webinar with your Cadence log-in (quick and easy registration if you don't have one).

Thuemmel first explained why listeners should consider using dynamic power analysis (DPA) at a system level. He noted that DPA can help engineers identify architectural issues early in the design flow, and analyze the system-level power impact of hardware/software interactions. Cadence Palladium Dynamic Power Analysis, he noted, is tightly coupled with the Cadence RTL Compiler for early power analysis.

Going Deeper with DPA

SoC power analysis, Thuemmel noted, requires "deep cycles." With simulation alone, he said, "you are running a limited number of cycles, so you may just encounter a peak and figure that this is your power consumption peak. If you run more cycles with Palladium XP, you may find out much later in the test scenario that you have your real peak."

So, how can one use DPA effectively in the design cycle? Bringing DPA into the RTL design flow is easy, Thuemmel said. Palladium XP users can generate a weighted toggle histogram, compute an activity profile, and bring results into SimVision for viewing and analysis (see diagram below).

The gate-level design flow for DPA is somewhat more complex but also more accurate. Here, users capture activity information in a TCF format (described below) and pass it to the Cadence RTL Compiler. This tool reads the same gate-level netlist that is running on the emulator, and it has power and switching activity values for the cells, memories and macros. Users can add parasitic information with a SPEF file. The result, said Thuemmel, is a "very accurate power estimation" displayed graphically in the SimVision waveform tool.

Thuemmel then described three types of DPA reports:

  • Native toggle count (NTC): NTC is easily generated by uploading the activity from a Palladium run. It is primarily used for early stage estimation and is less accurate than the other two methods, but report generation time is faster.
  • Weighted toggle count (WTC): While NTC assumes all the nets are the same with respect to power consumption, WTC recognizes that different nets have different impacts and "weights" them accordingly. It is more accurate than NTC but report generation is slower.
  • Toggle count format (TCF): TCF is the most accurate method, and it has the longest report generation time. TCF represents design activity for a given time window and for each design signal.

Finally, Thuemmel showed that DPA with Palladium is a flexible solution for hardware/software co-verification. Software developers can use familiar debuggers to set breakpoints, look at registers, change memory locations, and perform many other tasks. Engineers can run power analysis to better understand the software impact on power consumption. Thuemmel concluded his presentation with several customer success stories.

Speeding Low-Power Verification

Ake noted that low-power verification with Palladium XP is just one part of an integrated low-power solution provided by Cadence. Palladium XP, he noted, can play a role at several stages of the design process, including RTL low-power simulation, logical (synthesized) low-power simulation, and physical low-power simulation.

Ake also said that Palladium XP supports multiple low-power design methods including power shutoff (PSO), multiple supply voltages (MSV), and dynamic voltage frequency scaling (DVFS). He noted that Palladium use models including traditional in-circuit emulation, emulation with static or dynamic target, in-circuit acceleration, and simulation acceleration can all be used in conjunction with a low-power intent description and the user's RTL.

Palladium XP compilation is fast, Ake said, and power intent files are checked for syntax and semantics. Power-related instrumentation is added to the database during compilation to support behaviors like PSO. The fast compile allows rapid design turns. The diagram below shows how this happens.

Finally, Ake showed the Palladium Low-Power Verification GUI, which allows users to create debug expressions for the Palladium logic analyzer tool, get values of low-power objects, probe low-power objects, create a log file of low-power events, and display low-power detail in the "view" chosen by the user.

Again, you can access the webinar here. For a complete list of all archived webinars, click here.

Richard Goering

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Palladium XP II—Two New Use Models for Hardware/Software Verification


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