With a theme of "where the chip meets the board," DesignCon is the premier technical conference dedicated to signal integrity at the chip, board, and system levels. Produced by UBM Tech, DesignCon 2014 will be held January 28-31 in Santa Clara, California, and Cadence will have a strong presence at this year's event.
First, however, I'll give a quick general overview of DesignCon 2014, which consists of a technical conference and an exhibition (Expo). The Expo runs 12:45pm - 6:00pm on Wednesday, January 29 and 12:30pm - 6:00pm on Thursday, January 30. It features high-speed design tools and solutions for modeling and simulation, test and measurement, prototyping, analyzing, packaging, and more. Over 150 vendors will exhibit, and you will find the vendor list here. A free Expo pass will also get you into the keynote speeches and panels.
Highlights of the 2014 Expo include:
- Free education, speed training, and product teardowns in the Chiphead Theater
- The Agilent Education Forum on Wednesday and Thursday
- DesignTOUR prizes
- Welcome Reception at the Computer History Museum and Happy Hours at the Expo
Keynote speakers include Dr. Hermann Eul, Vice President and General Manager, Mobile & Communications Group, Intel (Tuesday): Eileen Bartholomew, Senior Vice President, XPRIZE (Wednesday); and Thomas Pawlowski, CTO and Fellow, Micron Technology (Thursday). At this writing, only a description of the Pawlowski speech is available. He will speak about three revolutions in memory architectures.
DesignCon Technical Conference
The DesignCon 2014 conference includes over 100 sessions across 14 tracks. One new track this year is Wireless and Photonic Design and Integration. Other tracks are as follows:
- Optimize Chip-Level Designs for Signal and Power Integrity
- Overcome Analog and Mixed-Signal Design and Verification Challenges
- Optimize System Co-Design: Chip/Package/Board
- Characterize PCB Materials and Processing Characterization
- Apply PCB Design Tools and Methodologies
- Design Parallel and Memory Interfaces
- Optimize High-Speed Serial Design
- Detect and Mitigate Jitter, Crosstalk and Noise
- Leverage High-Speed Signal Processing for Equalization and Coding
- Ensure Power Integrity in Power Distribution Networks
- Achieve Electromagnetic Compatibility and Mitigate Interference
- Apply Test and Measurement Methodology
- Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques
For a complete overview of the conference program, see the Schedule Builder here.
Cadence at DesignCon 2014
Last year at DesignCon, Cadence showcased the first integration of the Sigrity signal integrity and power integrity tools with Cadence Allegro PCB design tools (see photo below).
At DesignCon 2014, Cadence will hold ongoing demos of its Allegro Sigrity Integration (ASI) tools at booth #507. Visitors will be the first to see new features in ASI 16.63, including analysis and compliance checking for DDR4 interfaces. Demos in the Cadence booth will include constraint-driven power integrity design and analysis, power-aware memory interface design and analysis, multi-gigabit serial link design and analysis, and chip-package-board co-analysis.
Cadence experts will participate in the following technical sessions:
- Panel -- Brad Brim, product engineer, will speak at a panel discussion titled System-Level Power Integrity Tools Providers and Tool Users Engage. In this panel, tool providers and system integrators will discuss their views of power integrity in the design implementation and analysis flows. 3:45pm - 5:00pm, Wednesday Jan. 29
- Paper - Brad Brim teams up with Xilinx authors in a paper titled Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems. 10:15am - 10:55am, Thursday Jan. 30
- Panel - Ken Willis, product engineering director, will speak at a panel discussion titled Post-Equalization Metrics at 25 Gbps and Beyond. In this panel, SerDes developers and end users will discuss techniques and methods for measuring the eye at the output of the receiving equalizer. 3:45pm - 5:00pm, Thursday Jan. 30
- Paper - Joy Li, Jian-Hau Luo, and Yingxin Sun from Cadence will present a paper titled Power-Aware Buffer Behavioral Model with Overclocking Solution. 10:40am - 11:20am, Friday Jan. 31
For further information and registration, see the DesignCon 2014 website. Advance rates expire January 17. For more information on Cadence activities, click here. See you at the conference!
Related Blog Posts
Allegro Sigrity Makes its Debut at DesignCon 2013