Recognizing that video has become a key tool for explaining new technology, Cadence stepped up its video production in 2013. As a result, there are nearly 400 videos at the Cadence YouTube channel. This blog post provides an introduction to the channel and offers a sampling of some of the videos you'll find there.
The Cadence YouTube channel is located at http://www.youtube.com/user/CadenceDesign, and if you go there you will find the following listings:
What to Watch Next
- Recent Activity
- Success - Customers and partners highlighting collaboration and use of Cadence technologies
- Demos/How to Videos - step-by-step instructions and tips and tricks to help you get the most out of your Cadence solution
- Cadence Picks - Videos we think you will find most interesting and useful
- Recent Uploads
Additionally, if you like what you see, there is a button that allows you to subscribe to the channel.
Following are (in my opinion) some of the more notable Cadence videos that were posted in 2013. You can click on the video or click on the link to watch.
More Insight on Major Announcements
One of the best ways to understand a major announcement is to watch a video that explains it. The following videos explain three major 2013 announcements - the Tempus Timing Signoff Solution, the Voltus IC Power Integrity Solution, and Virtuoso Electrically Aware Design.
Addressing Today's Signoff Challenges with the Tempus Timing Signoff Solution
Hear from Anirudh Devgan, now Senior Vice President, Digital and Signoff Group at Cadence, as he talks about current challenges with signoff and how the groundbreaking new Tempus Timing Signoff Solution from Cadence addresses these issues.
New Power Signoff Tool: 10X Faster Performance and SPICE-Like Accuracy
Ready to speed up your design closure process? Watch this video to learn about a new power signoff tool from Cadence that delivers 10X faster performance than competitive solutions, with SPICE-like accuracy and capacity for up to one billion instances. Cadence's Anirudh Devgan walks you through three key benefits that you can enjoy by using the new Voltus IC Power Integrity Solution.
Accelerate Chip Design with Cadence Virtuoso for Electrically Aware Design
Hear from David White, Engineering Group Director at Cadence, as he talks about current design challenges and how the Virtuoso Electrically Aware Design Solution from Cadence addresses these issues.
Demos and How-to Series
What better way to learn about something than to see it in action? The Cadence YouTube channel features several popular how-to video series. Here's the introductory video for a series of 12 instructional videos, posted in 2013, that discuss Universal Verification Methodology (UVM) register base classes.
UVM Register Layer Basics 1 - Introduction
The Universal Verification Methodology (UVM) features register base classes and an associated methodology that enables you to program and verify your registers in a consistent and effective manner.
This video series is an introduction to the Register Layer (aka UVM_REG) of UVM for SystemVerilog IEEE1800. The series provides incremental learning of register layer concepts, features, architecture, and methodology.
Another set of instructional videos posted in late 2012 and early 2013 focused on the SimVision simulator user interface. This series of 13 videos begins with the following introduction.
SimVision Debug Video Series Introduction
A quick introduction to the types of videos that will form the series as well as the demo environment (RTL and verification environment) that will be used throughout the video series.
The Cadence YouTube channel also hosts two widely watched instructional series about UVM. While they were posted in 2012, they are continuing to be so popular that I'll mention them here. As of Dec. 17 2013, the SystemVerilog UVM introduction below had received 12,264 views, and the e language introduction had received 2,430 views. The two series include 25 SystemVerilog videos and 24 e language videos.
UVM SV Basics 1 -- UVM Introduction
Introduction to the Universal Verification Methodology (UVM) for SystemVerilog language (IEEE 1800). Features slides, code, and demos. Tutorial-style videos provide incremental learning of important UVM concepts, features, architecture, and methodology. Starts with UVM fundamentals and builds up a UVM environment bottom up.
UVM e Basics 1 - Introduction
Introduction to the Universal Verification Methodology (UVM) for e language (IEEE 1800). Features slides, code, and demos. Tutorial-style videos provide incremental learning of important UVM concepts, features, architecture, and methodology. Starts with UVM fundamentals and builds up a UVM environment bottom up.
Customer and Partner Success Stories
Success story videos allow you to see how other designers have solved difficult challenges using Cadence tools and IP. Here are a few of the most-viewed success videos of 2013.
Tapeout of the Industry's First Cortex-A Based 14nm/FinFET Chip With ARM, Samsung and Cadence
Dipesh Patel, EVP and GM, Physical IP Division at ARM; Ana Hunter, VP of Foundry at Samsung Semiconductor; and Chi-Ping Hsu, now Chief Strategy Officer for EDA and Chief of Staff at Cadence, discuss the collaboration between the three companies to develop the first 14nm FinFET implementation of the ARM Cortex-A7 chip.
2.2 GHz Performance on 28nm ARM Dual Core Cortex-A9 Processor
Shrikrishna Mehetre and Souvik Mazmunder from Open-Silicon talk about how they leveraged Cadence Encounter Technologies to reach 2.2GHz performance on a 28nm ARM dual-core Cortex-A9 processor.
Increased Trace Depth, Faster Upload and Time to Market for Zenverge
Kent Goodin, Executive Vice President of Engineering, highlights how Palladium XP II helped Zenverge gain an 80X increase of trace depth and 8X faster upload times, allowing the company to exceed time-to-market goals and engage with customers six months early.
Video Blog - Mixed-Signal Verification
Several Cadence Community blogs ran video interviews in 2013. Here's one of mine - a video interview on the topic of mixed-signal verification. You can see the complete blog post here.
DVCon 2013 - Neyaz Khan, Maxim, Discusses Mixed-Signal (MS-SoC) Verification
In this interview Neyaz Khan, distinguished member of technical staff at Maxim, discusses best practices for mixed-signal SoC verification -- the topic of a DVCon 2013 paper he co-authored.
The Cadence YouTube channel has a wide selection of videos, so there's sure to be something of interest. Happy viewing!