In 2013, Cadence Community bloggers published over 375 posts in categories including Industry Insights, Functional Verification, Fuller View, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation.
Below is a listing, in order, of the most-read 2013 Cadence Community blog posts as of December 11, 2013. One strong theme that this list reflects is keen interest in advanced node ICs and FinFETs. Memory technology is another area of interest, with two posts from the August MemCon conference. And several posts on the list provided new information about long-existing technology (OrCAD, Allegro, gate-level simulation).
Notes: This list includes only blog posts that were actually published in 2013, not posts from prior years. Most are from the first half of 2013, probably because they have had a longer period of time to accumulate page views. The first seven blog posts on the list are Industry Insights blogs. The following three are from other categories, as noted.
I hope you enjoy this look back at the most popular blog posts of 2013!
1. TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
Keynote speakers at the TSMC 2013 Technology Symposium on April 9 cited excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies. Speakers also cited promising development work with 10nm FinFETs and 3D die stacking.
2. Wide I/O 2, Hybrid Memory Cube (HMC)—Memory Models Advance 3D-IC Standards
Cadence announced the industry's first memory models for five emerging standards at MemCon on August 6. This blog post provides some background about two of those standards—Wide I/O 2 and Hybrid Memory Cube (HMC).
3. Functional Verification Survey—Why Gate-Level Simulation is Increasing
While some verification teams are moving to higher levels of abstraction with transaction-level modeling, a recent Cadence customer survey shows an increasing use of gate-level simulation. This blog post explains why.
4. BSIM-CMG FinFET Model—How Academia and Industry Empowered the Next Transistor
FinFET transistors promise tremendous performance and power advantages, but nobody can use them without an accurate compact model. The BSIM-CMG model from U.C. Berkeley provides just that—and Cadence and other industry partners helped develop it.
5. 10nm and 14nm FinFETs Pose Challenges—But Collaboration Brings Solutions
A presentation by Vassilios Gerousis, distinguished engineer at Cadence, discussed "second-generation" double patterning at 10nm, double-patterning-aware placement and routing, and FinFET design challenges. As explained in this blog post, Gerousis also showed a FinFET-ready custom design flow and discussed two recent tapeouts.
6. New Book: Analog Design and Simulation Using OrCAD Capture and PSpice
Dennis Fitzpatrick, a former Cadence engineer and now a lecturer at the University of West London in England, has written a book aimed at engineers, students, and anyone else who has an interest in using simulation tools for the design of analog circuits. This blog post provides a chapter-by-chapter review.
7. MemCon Samsung Keynote: New DRAM and Flash Memory Architectures are Needed
Bob Brennan, senior vice president of the Memory System Architecture Lab at Samsung Semiconductor, spoke about "New Directions in Memory Architecture" at the MemCon conference on August 6. This blog post summarizes his views about the future of DRAM and NAND Flash memory technology.
8. Introduction to Cadence Virtuoso Advanced Node Design Environment
On January 28, Cadence introduced the Virtuoso Advanced Node Design Environment for leading-edge custom/analog ICs. This Custom IC blog post by Hiroshi Ishikawa explains the new release in detail.
9. 25 Years of Innovation: Then, Now, and the Road Ahead
2013 marks the 25th anniversary of Cadence, and this Fuller View post by Brian Fuller sets some context for the event by looking at how far technology has come during that period—and what the next 25 years might bring.
10. Customer Support Recommended—Pin Swapping in Allegro Design Entry CIS and PCB Editor
In this PCB blog post, Naveen Konchada describes pin-swapping techniques in the Cadence PCB flow using Allegro Design Entry CIS as the front end and Allegro PCB Editor as the back end.
Thanks for reading Cadence Community blogs in 2013, and stay tuned as we move into another exciting year for the EDA and semiconductor industries. Your comments are always welcome.
Related Blog Post
Top Ten Cadence Community Blog Posts of 2012