Home > Community > Blogs > Industry Insights > semico panel on semiconductor ip ecosystem reducing cost and risk
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Semico Panel on Semiconductor IP Ecosystem: Reducing Cost and Risk

Comments(0)Filed under: EDA, Industry Insights, SoC, Semico, IP, Mixed-Signal, mixed signal, TSMC, Cadence, Mentor, Tensilica, semiconductor IP, IPextreme, Savage, IP subsystems, IP ecosystem, Rowen, Polychronopoulos, Kochpatcharin, Analog Bits, Semico panel, Semico Impact

Despite years of progress in both business models and technology, semiconductor intellectual property (IP) is still risky, costly, and difficult to integrate. Can the IP ecosystem relieve the pain while providing more complete hardware/software solutions? Four industry experts shared their opinions at a lively panel discussion at the Semico Impact conference Nov. 6, 2013.

The panel was titled "IP Ecosystem Solutions for Complex Systems." The moderator was Mahesh Tirupattur, executive vice president at Analog Bits. Panelists were as follows, shown left to right in the photo below:

  • Chris Rowen, fellow, Cadence (and founder and former CEO of Tensilica)
  • Jason Polychronopoulos, product manager for verification IP, Mentor Graphics
  • Warren Savage, president and CEO, IPextreme
  • Dan Kochpatcharin, deputy director of IP portfolio management, TSMC

"The premise of this panel is to talk about the high cost and risk of integrating IP," said Tirupattur in his introduction to the panel. "There is a massive chance of failure if you choose the wrong IP, the wrong supplier, the wrong fab, or the wrong process. One missing link breaks the whole chain." While every IP provider claims that their IP is pre-verified, "at the end of the day, integration is still a nightmare," Tirupattur said.

With the tone set, the panelists responded with gusto.

Opening Statements

Savage noted that IPextreme helps semiconductor companies bring their internal IP into the semiconductor supply chain. Five years ago the company started selling the Freescale ColdFire processor core, and eventually IPextreme decided to sell the whole ColdFire platform (see recent announcement here). By so doing, "we enabled the entire software ecosystem," Savage said. "The IP business is much more than selling cores - it's about selling complete solutions, and tying together the semiconductor ecosystem with the software tool providers and EDA companies."

Polychronopoulos noted that verification IP (VIP) lets companies reuse their verification infrastructure environments. This includes a test plan, test sequences, and coverage, and users can add design-specific versions of these components. Support for the Universal Verification Methodology (UVM) is key, as well as portability across engines, debugging, and silicon-proven VIP.

There's a paradox in talking about ecosystems, Rowen said. On the one hand, if an ecosystem foundation is stable for a long period of time, more and more ecosystem components will grow up around it. On the other hand, design teams want to differentiate. "You want to get all the benefits of an ecosystem, in terms of skills and tools and libraries," Rowen said. "But you don't want to just use the same foundation as everyone else."

"If Tensilica should be known for one thing," he added, "it is solving this paradox of ecosystems. You can have dramatic innovation and the creation of things never seen before, and at the same time you can leverage an effective ecosystem that has all the things you want out of an ecosystem."

At TSMC, Kochpatcharin tracks incoming tapeouts and looks at how customers are using IP. He noted that IP reuse is growing rapidly. Out of 3,500 hard IP blocks that TSMC has cataloged, 2,500 were used more than once. "That's a lot of reuse, but what are the headaches?" he said. "The big challenge is verification and the quality of the IP. If you use this IP, how do you know it will work?"

Kochpatcharin discussed a TSMC IP quality program that is "kind of like ISO 9000." It includes a physical review, design rule checking, IP validation, and silicon verification. An IP validation lab performs audits of IP customer silicon. "In summary," he said, "IP quality is number one."

Questions and Answers

Q: Where do you see the role of customers, IP companies, EDA vendors, and foundries looking three years forward?

Kochpatcharin: There will be a lot more collaboration. We need feedback from IP vendors very early, to make sure that the power and performance of chips is what they are looking for.

Savage: We're getting more involved with our customers' end customers in the specification of systems and performance profiles. Recently we've become more involved in quality aspects and safety certification, so we're getting involved with the end customer directly.

Rowen: There are three adjacent associations for IP - process know-how, automation know-how, and application know-how. It is natural for EDA and IP to grow closer together, because the EDA companies have a good bit of process know-how. You hope EDA has the automation know-how. The tricky one is the application know-how - it's increasingly valuable.

Q: As people move to more intelligent, programmable subsystems, how do ecosystems need to evolve?

Savage: What we found in subsystem IP is that people want to reuse the OSes and all the [software] things used on chips.

Rowen: Subsystems are a lively topic, first because everyone defines "subsystem" differently. Many subsystems are good, but only some make business sense when it comes to IP licensing. What a lot of people want in a subsystem is the integration of hardware and software. If you don't have the capability to reuse that particular combination of hardware and software, subsystems can look like a services business.

Polychronopoulos: When a customer is reusing a subsystem, they don't necessarily want to get involved in the verification but they somehow have to manage the complexity of this device. There are multiple tens of interfaces around it. We're developing tools that will allow them to connect to multiple interfaces.

Q: IP reuse has a technical dimension and a business model dimension. What is preventing a higher level of reuse?

Savage: I think technology advances have far surpassed business-level innovation. We're now licensing to system houses, and they may have never done an IP license before. They don't understand the business terms or the concept of royalties. A sales person who worked for me said that IP contracts are like snowflakes-no two are identical.

Tirupattur: Mixed-signal IP reuse is almost like an organ transplant. It just does not work perfectly. The specs look good but I want something different.

Chris Rowen's comment about the 2013 Cadence acquisition of Tensilica:

"The acquisition of Tensilica by Cadence is really a watershed, certainly from an IP business model perspective. It also takes the notion of automation to a new level. Traditional CAD companies manipulated gates. But now, increasingly, customers are manipulating processors and subsystems. A new generation of technology is required to do that. So now, Tensilica goes to the big stage."

Richard Goering

Related Blog Post

Semiconductor Industry Headed for Strong 2014: Forecaster



Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.