Home > Community > Blogs > Industry Insights > voltus massive parallelism speeds power integrity analysis and signoff closure
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Voltus – Massive Parallelism Speeds Power Integrity Analysis and Signoff Closure

Comments(0)Filed under: Industry Insights, Palladium, Virtuoso, Encounter, EDI, SoC, IP, SPICE, system on chip, signoff, IR drop, power analysis, leakage, electromigration, Virtuoso Power System, Encounter Power System, power rail analysis, EPS, EM, Sigrity, Encounter Digital Implementation, distributed processing, Tempus, multithreading, parallell processing, static power, dynamic power, voltage drop, signoff summit, dynamic power anlaysis, Zhao, powerr integrity, Voltus

Performance, capacity, accuracy. These are the three criteria that IC design teams want most in a power analysis solution. By using a massively distributed, parallel compute engine along with a hierarchical capability, the Cadence Voltus IC Power Integrity Solution - introduced Nov. 12, 2013 - promises breakthroughs in all three areas.

When running on 16 or 32 CPUs, the Voltus solution has shown a 10X performance gain over existing power integrity analysis solutions (which generally can't scale well beyond 4 CPUs anyway). For the largest ICs, hierarchy gives Voltus another boost, allowing the analysis of designs up to a billion instances. Finally, a "SPICE-level matrix" solver promises full SPICE accuracy on the power grid network.

Voltus is tightly integrated with the Cadence Tempus Timing Signoff Solution, a static timing analysis and optimization tool that was announced in May 2013. Voltus and Tempus work together to provide a unified electrical signoff solution that reports the impact of power integrity on timing.

So what are the challenges in power integrity, and how does Voltus solve them? Here's a more detailed look at the industry's newest power integrity solution.

Why Power Analysis is Tough

Power analysis and signoff are not getting any easier. The biggest challenge, according to Jerry Zhao, director of product marketing for power signoff at Cadence, is the increase in design size. Designers are putting more and more cores and intellectual property (IP) blocks onto system-on-chip (SoC) designs. A second challenge, he observed, is accuracy - mobile devices in particular have very low power, perhaps below 1V, so the noise margin on the power grid is very small.

Yet another challenge is the pervasive use of low-power design techniques, such as power domains and power gating. While earlier designs used two or three power domains, Zhao noted, some designs today use dozens of power domains.

Also, the list of "care abouts" in power analysis is growing. Just looking at static (leakage) or dynamic power is not enough. Analysis tools must also look at the in-rush current that occurs when a power domain is turned back on, and consider how long it takes for current to stabilize. IR drop (voltage drop) affects timing and is an increasingly important part of the analysis. Electromigration (EM) is becoming more important at advanced nodes. Finally, an early power rail analysis can pinpoint potential problems before placement and routing.

Analysis alone is not enough --- design teams must also fix any problems found during analysis before signing off. To allow this fixing, power integrity analysis tools should be closely integrated with IC implementation systems as well as IC packaging and PC board tools. Power analysis and optimization are not just chip problems, they are system problems.

How Voltus Can Help

Voltus supports both vector-driven and vector-less static or dynamic power calculation, as well as static and dynamic and power grid simulation for IR drop and EM. Zhao said that static analysis gives a good measurement of the average behavior of a power grid, whereas dynamic analysis is good for finding transients, such as a sudden spike in current.

Voltus will replace the existing Encounter Power System (EPS) tool. While the parallel part of the EPS engine has been completely rewritten, current EPS users will see the same user interface and use the same scripting they used before. EPS has some parallel capability but, like its commercial competitors, does not scale well past four CPUs.

Voltus, which supports both distributed processing and multi-threading, scaled well to 32 CPUs in early customer engagements and "we believe it can scale up to any number of CPUs," Zhao said. Even though Voltus uses massive parallel computation, its specialized solver still performs a full SPICE matrix solution across the entire circuit.

The new offering provides many types of power analysis. For starters, it does a power distribution analysis across the chip, including leakage power and switching power. Once it has the current information, Voltus can do an IR drop analysis on the power grid. It also provides  an EM analysis on the power grid. Voltus also analyzes signal EM that takes place on the signal wires.

A unique Voltus feature, according to Zhao, is early power rail analysis. With this feature users can start their power grid analysis at the floorplanning stage, before placement and routing. While not as accurate as post-route signoff analysis, this early power estimation can help designers avoid multiple iterations due to such problems as not having enough power switches. The rail analysis can also be done during the placement and routing stage with partial layouts.

An Integrated Analysis

While Voltus can work as a standalone product, it provides even more value when coupled with other Cadence tools. Voltus works with the Encounter Digital Implementation System to help users fix the problems that power integrity analysis finds. For example, if in-rush current is too strong, Voltus can recommend larger power switches and send the layout back to Encounter to fix the problem. Another common optimization would be the addition of decoupling capacitors.

Voltus links with the transistor-level Virtuoso Power System to enable the analysis of custom/analog IP in a mixed-signal SoC design. Another important interface is with the Palladium XP platform, which provides accelerated dynamic power analysis and can quickly generate stimulus that Voltus can use.

Voltus is also closely linked with the Cadence Allegro Sigrity power analysis tools, which bring in the package and the board. The Sigrity tools can generate a package model using SPICE or s-parameters, and hook it up with the chip for Voltus analysis. "That's the most accurate way to analyze chip-level power signoff," Zhao said. "Without all the pads tied to the package model, it is not accurate."

One capability that may be very important in the future is support for 2.5D and 3D IC thermal modeling. Voltus can create a power map file for the dies in a 3D stack. The Sigrity PowerDC tool will read this map to do a thermal analysis.

The most important linkage, however, may be between Voltus and Tempus. Taken together, these two products can offer a unified electrical signoff solution. That's important because power integrity directly affects timing, which is sensitive to power supply changes. As Zhao explained, "with voltage drop, delays are going to increase and paths may fail. We are able to analyze all the voltage drops at the window in which your static analysis is going to run." The alternative to this kind of analysis, he noted, is using excessively pessimistic guardbands.

You can learn more about Tempus and Voltus at the Cadence Signoff Summit Nov. 21 at Cadence San Jose headquarters. To read a feature story, click here.

Richard Goering

Related Blog Post

Tempus - Parallelized Computation Provides a Breakthrough in Static Timing Analysis


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.