System-on-chip (SoC) performance analysis is typically performed today by system architects using highly abstracted SystemC models. At ARM TechCon last week (Oct. 29, 2013), Cadence pioneered a different approach by announcing the availability of Interconnect Workbench, a performance analysis solution that uses automatically generated interconnect RTL along with traffic profiles for peripheral IP.
The Cadence® Interconnect Workbench is a performance analysis and functional verification solution for ARM® CoreLink™ System IP SoCs. It provides cycle-accurate measurements of transaction latency and bandwidth on cascaded interconnects, and it allows users to run and compare many "what if" architectural and traffic scenarios in a single day. Secondly, it automatically generates a Universal Verification Methodology (UVM) e language or SystemVerilog testbench, and configures the verification IP (VIP) that applies stimulus and response to the interconnect.
The diagram below shows how the Interconnect Workbench works. It takes in automatically generated interconnect RTL and an IP-XACT metadata description from the ARM AMBA® Designer. Interconnect Workbench works with SoCs using any combination of the AMBA protocols and supports traffic profiles for them. The Interconnect Workbench then builds either a performance-oriented or a verification-oriented testbench.
The Cadence Interconnect Validator product (previously called Interconnect Monitor) captures performance metrics and runs verification checks. It is an "underlying and required technology" for using Interconnect Workbench, according to Avi Behar, Cadence product marketing director for AMBA and interconnect VIP. However, Interconnect Validator is not an automated solution. The Interconnect Workbench provides the automation and graphical analysis capabilities.
For performance analysis, Interconnect Workbench adds AMBA traffic generators and a performance monitor to the testbench. Instead of using SystemC models or RTL blocks of the peripheral IP, users connect a traffic generator or "proxy" to the master and slave ports.
What's new with the Interconnect Workbench?
Much of what is written above was covered in a blog post I wrote last year previewing the Interconnect Workbench. But now that the product is shipping and receiving customer feedback, some key improvements have been made.
"One thing that we've been working with ARM on quite a bit is a more systematic approach to performance analysis of complex systems," said Nick Heaton, distinguished engineer for Cadence R&D. He said that Cadence has built some new automation into the Interconnect Workbench that allows users to systematically characterize their paths through the SoC. The tool can generate a complete characterization test suite and step through every path in the system, revealing the maximum bandwidth and the minimum latency that will ever appear on each path.
The Interconnect Workbench also has a completely new GUI that provides more interaction with users, and is scalable up to millions of transactions. Another new capability is the use of "performance checks." Much like formal assertions, these checks could ensure (for example) that bandwidth will never fall below a given level. The checks are typically run as a batch process, and the tool produces an HTML report that pinpoints any failures.
Why cycle accurate?
According to Heaton, there's a simple reason for using cycle-accurate RTL for interconnect performance analysis—"you can't get accurate measurements out of anything else." And it's really not a big restriction, since design teams usually have interconnect RTL available relatively early in the design cycle.
However, RTL is not needed for peripheral functions—nor is SystemC. Interconnect Workbench can use highly abstracted traffic profiles, which generate "traffic that is not 100% real but is realistic enough for performance analysis," said Steve Brown, product marketing director for Interconnect Workbench at Cadence. Real software is not required. The use cases specified with traffic profiles on the ports of the interconnect gives users enough information to optimize the performance of the system.
"Our challenge is to re-educate the market that you can do very effective performance analysis without having to build complex SystemC models," Brown said. "That has usually been the barrier to adoption of these technologies. They [the models] just take too long to build."
One question now is who is going to use the performance analysis features of Interconnect Workbench. For now, Heaton said, it's mostly verification engineers, because they are most experienced with cycle-accurate simulation. But he predicted that the tool's performance analysis capabilities will "move up the food chain" to architects, and come into play earlier in the design cycle.
Meanwhile, Interconnect Workbench gives verification teams capabilities they never had before. Brown noted that verification engineers have to make decisions "that are potentially lower level than high-level architectural decisions, but still have a lot of impact." Examples might include choosing IP configuration options and selecting the depth of FIFOs. It may take hundreds of simulations to get the information that's needed to make a good decision. Interconnect Workbench can run those simulations and present the data in a usable way.
Getting the word out
Interconnect Workbench was featured in two technical sessions at the recent ARM TechCon conference:
- Wed., Oct. 30, 10:30am: How to Measure and Optimize the System Performance of a Smartphone RTL Design. Nick Heaton (Cadence) and William Orme (ARM).
- Thurs., Oct. 31, 11:30am: Verifying the AMBA4 ACE Protocol—At the Interface and Across the Interconnect. Yoav Lurie (Cadence) and William Orme (ARM).
The Cadence web site has further information about Interconnect Validator and Interconnect Workbench. You can also read a feature story about Interconnect Workbench. The ARM website has information about the AMBA Designer.
Finally, join Cadence technical experts for a live, on-line chat about interconnect design and verification Wednesday Nov. 6, 2013 at 11:00am Pacific time, or view the archived talk afterwards.
Related Blog Posts
Designer View: SoC Interconnect Analysis—What We're Doing, What's Still Needed
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs