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Spectre XPS – Cadence Reinvents FastSPICE Simulation

Comments(0)Filed under: Virtuoso, spectre, Mixed-Signal, ADE, SPICE, analog/mixed-signal, parasitics, SRAM, power gating, John Pierce, Fast SPICE, PVT corners, hierarchy, memory characterization, circuit simulation, partitioning, Spectre XPS, Liberate MX, XPS, FastSPICE

Last year I wrote a blog post suggesting that FastSPICE simulation technology is "hitting the wall." A new approach is clearly needed, and Cadence is responding this week (Oct. 9, 2013) with Spectre XPS (eXtensive Partitioning Simulator), a FastSPICE simulator that sets new milestones for speed, capacity, memory footprint, integration, and ease of use.

FastSPICE is a transistor-level simulation approach that provides significant performance gains over full SPICE simulators, which must (unlike FastSPICE) solve a full matrix solution for the entire circuit under test. FastSPICE simulators may use techniques such as model reduction, event-driven simulation, multi-rate simulation, and hierarchy, and they typically partition the design into smaller sub-circuits that can be solved individually.

However, older FastSPICE simulators are running into problems with partitioning and hierarchy. Power gated architectures - very common today, with the demand for low-power circuits -- break the partitioning techniques used in older FastSPICE engines. Increasing RC parasitics make it difficult to use hierarchy, and slow the simulation because of the additional data that must be managed. Finally, increasingly complex advanced-node circuits result in memory, capacity, and performance demands that older FastSPICE simulators cannot meet.

Spectre XPS Uses Advanced Partitioning

Cadence is responding to these challenges with Spectre XPS, which uses advanced partitioning techniques that promise 10X faster throughput while requiring 2X-3X less memory than competing solutions. Spectre XPS can manage advanced-node parasitics and power gated architectures. It provides tight integration with the Cadence Spectre simulation platform, Virtuoso Analog Design Environment (ADE), and Liberate MX memory characterization tool. The current release of Spectre XPS is aimed at SRAM characterization, and mixed-signal SoC support is coming soon.

As shown below, Spectre XPS is based on the same simulation infrastructure as the SPICE-accurate Spectre simulator, Spectre RF, and Spectre APS (Accelerated Parallel Simulator). All these simulators use the same simulation database, front-end parser, and device library. A common model interface supports MOSFET, silicon-on-insulator (SOI), bipolar junction transistor (BJT), Verilog-A, and proprietary device models. A common simulation front end takes in SPICE netlists, Spectre netlists, and DSPF/SPEF format files. The environment provides RC reduction and supports static and dynamic checking.

According to John Pierce, product marketing director for circuit simulation at Cadence, it isn't quite correct to say that Spectre XPS is "integrated" with Spectre. "It is Spectre," he said. Invoking XPS, APS, or any other Spectre simulator requires only a command-line prompt from a common user interface.

Spectre XPS is also tightly integrated with ADE, which provides analog/mixed-signal simulation control and management. Given that many foundries use ADE to build process design kits (PDKs), ADE will provide a close connection to the mixed-signal SoC ecosystem, Pierce said.

Ease of use was a major development criterion for Spectre XPS. In previous generation FastSPICE simulators, Pierce observed, designers would often go block-by-block setting various simulation options. With hundreds of blocks and many potential options, the list of options can go on for pages. Spectre XPS users, on the other hand, will identify the type of circuit (such as SRAM) and they will have one speed dial they can set.

"That's it," Pierce said. "We're going to have the tool handle everything under the hood. We are really focused on streamlining the adoption of XPS."

Another Spectre XPS feature is its ability to consider the impact of IR drop on timing. IR drop (voltage drop) reduces drive strength and can cause a timing variation of up to 10 percent. Today, however, FastSPICE users separate the power network from the design, solve them separately, stitch them back together, and get the results. The advanced partitioning algorithm in Spectre XPS allows a simultaneous IR drop and timing solution. This can help designers reduce timing margins.

Spectre XPS and Liberate MX for Memory Characterization

As noted, the initial release of Spectre XPS focuses on SRAM characterization. Given the high embedded memory content in today's SoCs, memory characterization - which delivers the timing and power views that designers need - is a critical step. ROM, RAM, and multi-port register files can take up half of the die area of a modern SoC. Current ad-hoc approaches do not accurately model timing, noise and power, and tools are struggling to support a full range of process, voltage, and temperature (PVT) corners.

FastSPICE can accelerate memory characterization, but only if the FastSPICE simulator and the memory characterization tool are tightly integrated. That's the case with Spectre XPS and the Cadence Liberate MX characterization tool, according to Pierce. He noted that designers can use Spectre XPS in standalone mode during design and then "plug it into" Liberate MX when it's time to do the characterization. Spectre XPS can perform a high-capacity simulation of a power-gated SRAM architecture with full parasitics.

Further information about Spectre XPS is available at a landing page.

Richard Goering

Related Blog Post

Is Fast SPICE Simulation Hitting a Wall?

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