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TSMC OIP Forum: 16nm FinFETs, 3D-ICs Gain EDA and IP Support

Comments(0)Filed under: EDA, Industry Insights, IC Design, Double Patterning, 3DIC, TSMC, 20nm, 3D IC, 3D-IC, Cadence, extraction, SRAM, 2.5D, foundation IP, FinFET, OIP, electromigration, CoWoS, EM, static timing analysis, Hou, Open Innovation Platform, 16nm, Cliff Hou, Jack Sun, TSMC OIP, 3D-IC reference flow, SRAM compiler, ESD, electrostatic discharge, Ecosystem Forum, InFO, RC extraction, 16nm IP, latchup, 16nm reference flow, wafer-level packaging

Two emerging semiconductor technologies - 16nm FinFET design and 3D-ICs - are moving closer to volume production, according to Dr. Cliff Hou, vice president for R&D at TSMC. Speaking at the TSMC Open Innovation Platform® Ecosystem Forum (TSMC OIP) Oct. 1, 2013, Hou (right) said that the EDA and semiconductor IP ecosystem needed to support those technologies is nearly complete, although work continues in a few challenging areas.

Hou was the second keynote speaker at the one-day conference in San Jose, California. The first speaker was Dr. Jack Sun, vice president of R&D and CTO at TSMC. Sun offered a progress report on TSMC's work with 20nm SoC, 16nm FinFET, and 3D-IC technologies, and you can read about Sun's talk in Brian Fuller's blog post.

As he started his talk, Hou noted that the TSMC 20nm SoC process (with planar transistors) is in mass production now, and 16nm FinFET is on track for "risk production" by the end of 2013. TSMC just completed the SPICE V0.5 release for 16nm, and expects the V1.0 release by the end of 2013. EDA tools and flows have been qualified, foundation IP has been validated, and interface IP is under development.

Tool and IP validation is not an easy task. Hou noted that a "more rigorous validation methodology" is needed for 16nm EDA solutions, and that the validation must not only encompass individual tool features but consider entire flows. Tool integration is a must. "One individual tool does not guarantee success," Hou said. "We have to make sure all tools are optimized in the same direction, and that you've got consistent results across different design stages."

Challenges for 16nm FinFET Design

Hou showed detailed checklists that depict the readiness of different EDA tools for 16nm FinFET technology. He identified several areas of particular concern, including the following:

  • RC Extraction. Because FinFETs are "3D" structures, RC extraction tools must accurately extract parasitics while maintaining the same end-user experience as planar extraction.
  • Electromigration (EM). The higher drive current of FinFETs raises EM susceptibility. In collaboration with EDA partners, TSMC has been able to relax EM rules by 4X while maintaining the same level of reliability compared to previous processes.
  • Static Timing Analysis (STA). FinFETs normally run at much lower voltages than planar devices, and this poses challenges for existing STA engines. One consideration is that path-based analysis must correlate well with SPICE simulation.
  • Electrostatic Discharge (ESD) and Latchup Checks. These have become increasingly important with advanced nodes, and TSMC now provides all ESD rules in one deck.

The good news is that nearly all of the required EDA capabilities in the digital IC flow are ready for the V0.5 release spec. One exception is the low Vdd STA accuracy mentioned above. Today, if you run a FinFET at (for example) 0.5V, the timing analysis numbers will be too conservative, Hou noted. "There is too much penalty on the design area, and that is why we're still working with design partners," he said.

Hou also noted that the entire flow for 16nm - as well as 20nm planar technology - must be "double patterning" aware. This is a situation where just upgrading an individual tool will not work. Tasks including standard cell layout, power planning, placement, routing, and dummy metal insertion must take into account the need for extra masks in order to print features correctly. "Without this kind of integrated verification, the solution will not work," Hou said. Fortunately, the double patterning aware flow is now "pretty efficient," he said.

Going Full Custom with 16nm FinFET

On the custom side, Hou said, 16nm FinFET technology requires new features in schematics and PCells (parameterized cells). Designers must be able to automatically generate a layout, verify it with layout-versus-schematic (LVS) checking, and run a post-layout simulation. The number of fins, NFIN, becomes an important parameter in the design flow. Hou said that the 16nm FinFET custom EDA flow is mostly complete, although EM requires more work with partners.

Hou also spoke about the "foundation IP" - the standard cells, memories, and I/Os - that are needed to design any system-on-chip (SoC). He said that a 9-track standard cell library is ready for release with the V0.5 spec for 16nm FinFET, with V1.0 support to follow in Q1 next year. A base library of 300 cells has been functionally validated, and TSMC expects a library of 1,000 cells to be available by the end of this year.

A 16nm SRAM compiler offering includes support for one-pole, two-pole, ROM, and double patterning devices. An ultra-high density feature can reduce chip area by 25-30%, and a full-custom cache can reduce area by 20%. Hou said that memory compilers are functionally validated and ready to go into silicon validation.

Foundation IP for 16nm FinFET also includes a 1.8V I/O with ESD latchup protection, and a 3.3V I/O that's currently under development. The development of interface IP, Hou said, "will be based on customer schedule and product requirements." If a particular piece of IP isn't on the schedule soon enough, "you can contact TSMC and we can work together with our IP partners to try and meet your schedule."

Looking Up to 3D-ICs

Hou also cited "very good progress" in 3D-IC technology. Last year TSMC announced CoWoSTM, its Chip-On-Wafer-On-Substrate process. This is a "2.5D" architecture in which multiple chips are placed side by side on a silicon substrate.

In 2013, Hou said, TSMC worked to ensure that CoWoS can handle high-bandwidth memory (HBM). He noted that TSMC demonstrated the ability to integrate an SoC chip with HBM in a CoWoS package. Further, TSMC is increasing the reticle size. Hou said the company has demonstrated a chip with a 26mmX48mm silicon interposer and a 60mmX60mm substrate.

TSMC's InFO (Integrated FanOut) wafer-level packaging offers many of the advantages of a silicon interposer architecture, with less density and lower costs. Hou noted that this multi-chip approach can replace a traditional POP (package on package) device and provide a smaller form factor, better signal-to-noise ratio, and improved thermal characteristics. Best of all, perhaps, is the price - 1 cent per square millimeter. While it now supports 600 pins, this total will go up to 3,600 next year. Hou predicted that InFO "will be a very disruptive technology for many applications."

Hou concluded by noting that the TSMC OIP has over 100 partners, including EDA, IP, and services providers. "There are more and more design challenges," he said. "We need to collaborate and leverage each other's expertise. The ecosystem plays a very critical role for us to work together to overcome these challenges."

(Note: On September 18, 2013, Cadence and TSMC announced the latest Cadence 3D-IC reference flow for true 3D die stacking. Cadence also announced that its digital and custom/analog tools have been included in TSMC reference flows for 16nm FinFET designs.)

Richard Goering

Related Blog Posts
Note: The TSMC 2013 Symposium is a separate event held in April 2013.

TSMC OIP: On the Road to the Silicon Super Chip

TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies

TSMC 2013 Symposium: Morris Chang Overviews Semiconductor Market, TSMC Progress

Photo from Taiwan Semiconductor Manufacturing Co. Ltd.

 

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