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TSMC 3D-IC Reference Flow Supports 3D Die Stacking

Comments(0)Filed under: Industry Insights, Virtuoso, Encounter, EDI, FinFets, Allegro, SKILL, stacked die, 3D, TSV, TSMC, 3D IC, 3D-IC, Cadence, QRC, wide i/o, 2.5D, Encounter Test, PVS, CoWoS, Sigrity, Encounter Digital Implementation, 16nm, reference flow, 3D stacked die, Tempus, XCitePI, TSMC OIP, PowerDC, 3D-IC reference flow, TSMC Ecosystem Forum, foundry flow, micro-bumps

An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the latest Cadence 3D-IC reference flow for true 3D die stacking (right).

While there has been considerable interest for several years in "3D-IC" technology, most of the implementation work to date has involved "2.5D" packaging, in which dies are placed side-by-side on a silicon interposer substrate. Cadence last year announced a collaboration with TSMC to develop tool support for that company's Chip-on-Wafer-on-Substrate (CoWoS) process. The Sept. 18 announcement, however, supports configurations in which dies are stacked on top of each other and connected with through-silicon vias (TSVs).

3D die stacking can provide tremendous advantages in memory bandwidth, power savings, and form factor minimization. This technology is already used by some memory providers. However, heterogeneous (logic plus memory, digital plus analog) implementations may still be several years away from volume production. There are still unresolved technology issues, such as thermal challenges, and ecosystem issues, such as who takes responsibility when things go wrong.

So why come out with a 3D stacked-die reference flow now? According to Brandon Wang, program management director at Cadence, the tool enablement must evolve with the technology. "We're looking at real production in a few years, and the reference flow has to be there before design activity starts," he said. The flow was qualified with a memory-on-logic design based on the Wide I/O interface.

What's in the Flow

Tools in the Cadence 3D-IC flow span digital, custom/analog, packaging, and signoff technologies. Some of the tools listed below, such as Encounter Digital Implementation System and Virtuoso Layout Editor, have 3D options. In such cases, Wang noted, designers can stay within the cockpit of the tool they've been using. Other tools, including the recently announced Tempus Timing Signoff Solution, already handle 3D die stacking and don't need a 3D option.

The Cadence 3D-IC flow includes the following:

  • Encounter Digital Implementation System
  • Encounter Power System (EPS)
  • Encounter Test
  • Physical Verification System (PVS)
  • QRC Extraction
  • Tempus Timing Signoff Solution
  • Virtuoso Layout Editor
  • Allegro System-in-Package (SiP)
  • Sigrity XcitePI (early chip power planning, I/O and core power model extraction)
  • Sigrity PowerDC (electrical/thermal co-simulation, hotspot detection, and signoff)

Sigrity PowerDC can provide electrical and thermal co-simulation for PCBs and IC packages, including 3D stacked die implementations.

A detailed overview of Cadence 3D-IC capabilities is provided at the Cadence website. These capabilities include 3D implementation (placement, optimization, routing) for custom and digital, 3D verification and analysis, design for test (DFT), IC/package co-design and system analysis, and 3D-IC semiconductor IP such as the Wide I/O controller and PHY.

On the digital implementation side, the Encounter Digital Implementation System provides a "double sided aware" methodology that includes TSV-aware, 3D floorplanning; optimization of blocks, TSVs, and micro-bumps to improve performance and power; multi-chip visualization with background views; and connectivity extraction maintained through TSV connections.

On the custom/analog side, the Virtuoso environment supports 3D-IC TSV/back-side connectivity, adjacent die stacking and debugging, routing to micro-bumps and TSVs, bump file transfer support, and multi-die visualization with background views. 3D extensions to extraction and analysis tools make it possible to consider parasitics for TSVs, micro-bumps, and interposer routing, and to analyze timing, power, thermal, and signal-integrity across multiple dies. Finally, IC/package co-design tools support 3D visualization and I/O feasibility planning between the chip, package and board.

Empowering Design with FinFETs

Also on Sept. 18, Cadence announced that its digital, custom, and signoff flows have been included in TSMC's 16nm FinFET Reference Flows. The digital flow includes Encounter Digital Implementation System, Encounter RTL Synthesis, Encounter Test, Physical Verification System, QRC Extraction, and Encounter Power System. The custom/analog flow incorporates optimized 16nm native SKILL process design kits that enable new capabilities in the Virtuoso platform, including FinFET placement using Modgens (module generators) and FinFET auto-alignment and abutment.

Reference flows are essential for new technology development, and the TSMC flows for 3D stacked die and FinFETs will help move these technologies forward towards volume production. You can learn more at the TSMC Open Innovation Platform (OIP) Ecosystem Forum October 1, 2013 in San Jose, California.

Richard Goering

Related Blog Posts

TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies





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