As you would expect with a new release of a hardware acceleration and emulation environment, the Cadence Palladium XP II Verification Computing Platform -- announced Sept. 9, 2013 -- is faster and has more capacity than its predecessors. What you might not expect is that the Palladium XP II enables two new Cadence System Development Suite use models for hardware/software verification.
Both the Palladium XP II platform and the Cadence Virtual System Platform are key components of the System Development Suite, and in the new hybrid use model they come together in combination with fast processor models running on a host workstation. Customer experience shows that hybrid mode users can boot an operating system up to 60X faster, and run hardware/software verification up to 10X faster, compared to conventional emulation use models.
In the second new use model, embedded testbench, designers "virtualize" the system environment by bringing system components into the Palladium box as software models. They run significantly faster than the physical components and are a lot easier to deal with than a tangle of cables, wires, rate adapters, PC boards, and peripherals.
Virtual Platform Models and Acceleration
The hybrid solution brings together the Virtual System Platform, the Palladium XP II, Cadence Accelerated Verification IP (AVIP), and "some additional smart technology that makes the communication and synchronization between the virtual world and the hardware world much easier," according to Frank Schirrmeister, group director for product marketing for the System Development Suite at Cadence. The hybrid mode can use standard communications mechanisms such as the Accellera SCE-MI interface.
Conventional wisdom holds that you want to put as much as possible into the Palladium box, because whatever runs on a host workstation will be slower. In this case, however, processor models running on the host are significantly faster. Remember that virtual platform processor models are designed for speed. While the Palladium runs in the MHz range, processor models on the host can run in the 20-50 MIPS range. Moreover, Schirrmeister noted, the processor models on the host can use just-in-time compilation techniques.
The hybrid mode then allows developers to take pieces of the design that are inherently parallel - such as graphics or video decoders - and run them on the hardware accelerator. Also, if there are portions of the design that require more accuracy for software development, the full RTL version can run in the accelerator.
There are several motivations for using hybrid mode. A Palladium user can run hardware/software verification a lot faster than he or she could with emulated RTL processor models. A virtual platform user can take legacy RTL and run it on Palladium rather than writing a new model for the virtual platform. A third motivation is to offload capacity to the host, freeing up more space in the Palladium platform.
At the Cadence Theater at the Design Automation Conference (DAC) in June 2013, Alex Starr of AMD presented what he called "virtual platform co-emulation" with Palladium. This is essentially the hybrid mode, and it gave AMD a 2-20X performance improvement over conventional emulation. It also provided a familiar debugging environment for software engineers. You can read more in my previous blog post, and you can access an audio presentation with slides.
Embedded Testbench - Thinking Inside the Box
With the embedded testbench mode, you move the system environment into the emulator box for faster execution. For example, instead of using a physical USB device hooked up to a SpeedBridge rate adapter, you would represent it as a software model running on a dedicated test processor that is connected to Cadence AVIP. This gives you, in effect, an advanced synthesizable testbench.
However, the entire testbench does not need to be synthesizable - just the test processor and its environment. The tests themselves become software routines running on the test processor. "The testbench is often not synthesizable," Schirrmeister said. "That's where the embedded test model comes in quite nicely. Instead of having to write the responses of all the peripherals, you synthesize the test processor once, and then develop software representing all the [peripheral] models, like USB, that the chip talks to."
Even though more of the system environment moves into Palladium, debug capability is still strong, Schirrmeister said. In contrast to FPGA-based emulators, he said, the processor-based Palladium has full visibility into the design and lets users probe every node.
At the Cadence DAC Theater, Mehran Ramezani of Broadcom described the "embedded testbench" methodology his company has adopted with Palladium. He noted that Broadcom engineers can develop device drivers ahead of the silicon, debug software that is supposed to be ready when the silicon arrives, measure performance, find problems in RTL, and enjoy good visibility into the device under test. You can read more in my previous blog post and access an audio presentation with slides.
Bigger, Faster, Better
So what else is new with the Palladium XP II announcement? Here's a short list:
- Extended capacity up to 2.3B gates and 512 concurrent users
- 2X improvement in tracing capability
- 3X increase in trace upload bandwidth
- 2X the debug productivity of previous generations - 5X that of competing systems
- New accelerated verification IP (AVIP) protocol support - DSI 1, CSI 2, HDMI, AHB, APB, SRIOV, PCIe, I2C, SimCard, Keypad, and Ethernet
- Higher fidelity and faster Dynamic Power Analysis
Further information is provided on a web page at Cadence.com.
Related Blog Posts
Designer View: New Emulation Use Models Employ Virtual Targets
Designer View: Embedded Palladium Testbench Speeds System Bring-Up
Related Article - System-Level Design Community
What Really Matters: User Care-Abouts in Hardware-Assisted Verification