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Programmable Memory BIST– A New Direction for Design for Test (DFT)

Comments(0)Filed under: Industry Insights, DFT, Encounter Test, MBIST, design for test, memory BIST, Petrakis, JTAG, built in self test, PMBIST, user-defined algorithms, rapid adoption kit, memory test, Gallagher

Memory built-in self test (MBIST) is a design for test (DFT) methodology that has been around for many years. But until now MBIST algorithms have generally been hardwired -- they can't be changed once the design has been built.  A new methodology available in the Encounter Test 12.1 release, programmable MBIST, promises to give IC designers much more flexibility.

While programmable MBIST provides benefits at any process node, it is especially helpful at 28nm and below, and will be extremely valuable for upcoming FinFET technology nodes, according to Bassilios Petrakis, product marketing manager for Encounter Test. With sub-20nm complexity, he observed, "you want to be able to adapt the algorithm depending on the situation you have."

"For a new node and technology (transistor) structures, you don't always know what the failures are going to be, or what type of [test] algorithm is really optimized for the technology," said Patrick Gallagher, architect at Cadence. "You can go in with a set of canned algorithms, but if you're getting failures you can fine-tune those algorithms [with programmable MBIST] to something very specific for your technology and your memory design." This level of flexibility allows designers to adapt to the problem at hand.

Building Block Approach

The silicon-proven programmable MBIST architecture allows users to load new algorithms with no penalty. "Algorithms are more than just programmable, they are user defined," Gallagher said. "And we have built in syntax so you can describe to the application how you want the algorithms to run, and you can create any algorithm you want."

The programmable MBIST also comes with 30-40 predefined algorithms that are built into the application. These can be converted into hardwired algorithms to save area - just like the programmable algorithms and the user-defined algorithms, as shown below. Conversely, predefined algorithms can be reprogrammed and run through a JTAG interface. Whether hardwired or JTAG, the tests will run at speed.

A collection of algorithmic "building blocks" allows the programmability. For example, a user could pick a given "march" algorithm that runs 1s and 0s through a memory address space. Users can change backgrounds, sequences, address increments, and more. The illustration below provides an example.

The programmable MBIST building block structure is shown below. Each block can be shared for different levels of flexibility and performance tradeoffs. One Algorithm Memory Unit (AMU) can be shared across multiple Sequence Iterator Units (SIUs), which can be shared to test multiple memories. These shared components pose no limitation on the testing of the memories, except for physical limits. Tests can be done in parallel or serial even with shared components.

Sharing the Data Compare Unit (DCU) involves a tradeoff. The DCU can be shared across multiple read ports and memories, but designers will trade off area for test time, forfeiting what can be tested in parallel for area savings.

One benefit, said Gallagher, is area savings. "We have found that we're getting another 15% to 20% area reduction on top of our standard offering for the same functionality, so we're getting more functionality with less area."

Memory Views

Gallagher noted that the programmable MBIST architecture reads in "memory views," which describe the memory in terms of port descriptions, address manipulation, physical structure, and redundancy structure. Cadence is working with memory vendors on generating memory views.

A "configuration file" contains the information about how to test the memories, and contains the directives that control the insertion of programmable MBIST logic into the netlist. It describes how the targeted memories must be tested, provides information needed to construct the programmable MBIST building blocks, and creates a test plan.

An upcoming Encounter Test release will provide a direct access method for programmable MBIST. Going beyond today's JTAG access method, this provides a minimal pin support solution for the programmable MBIST, which is often required for mixed-signal designs where digital pins are at a premium. JTAG access will still be needed for programmable support.

The programmable MBIST capability can be used at any process node. A Rapid Adoption Kit is available at support.cadence.com to help customers test drive or ramp up on this technology.  Gallagher described programmable MBIST in a presentation at CDNLive Silicon Valley 2013. To download the presentation, click here for CDNLive proceedings (Cadence log-in required). After you've logged in to the proceedings, select "Front End Design" and look for session FED105.

Richard Goering



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