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Interview with Lip-Bu Tan, Part 1 – How Cadence is Positioned to Build Upon Success

Comments(1)Filed under: EDA, Industry Insights, Palladium, ESL, verification, IP, Lip-Bu Tan, Denali, Cadence, Tensilica, signoff, Azuro, Tan, system-level design, electrically-aware design, Sigrity, Tempus, EAD, Cadence reorganization, acquisitions, Lip-Bu

Under the leadership of Lip-Bu Tan, Cadence President and CEO, Cadence has experienced strong growth during the past four years. In addition to steadily growing its revenue and hiring hundreds of new R&D engineers, Cadence has enhanced its product lines, built an impressive intellectual property (IP) portfolio, and improved customer and partner relationships. Now Cadence is gearing up for the next phase of growth with an organization based on four business units - System and Verification Group, Custom IC and PCB Group, Digital and Signoff Group, and the IP Group.

In this interview, the first of a two-part series, Tan discusses the success of the last four years. He talks about acquisitions, explains the strategy behind the four business groups, and notes Cadence plans to "double down" in functional verification. This interview will be continued in a blog post by Brian Fuller.

Q: Cadence has been very successful during the past four years, with steadily increasing revenue and a growing staff. What's the secret to that success?

A: It all starts with culture change. I'm a big believer in culture change. If you want to shift direction you have to change it from the heart.

To begin with, we emphasize integrity and accountability. Secondly, to build strong customer relationships we respond quickly, and we listen to the customer very closely. I spend most of my time in front of customers. I want to be their trusted partner, to provide the best tools and solutions, and to help them work through some of the most challenging designs they have.

At Cadence, it's very important for us to work as one team, even though we have different functional groups. We work in an environment of deep trust, and people don't have to be afraid of making mistakes.

We are growing our culture of innovation and we strongly encourage creative ideas. The other thing that's very important is our quality initiative. Everybody works together to make sure we have the best quality, and I make sure we deliver the quality.

Q: Cadence has done some acquisitions recently, especially in the IP area. What's driving these acquisitions, and is Cadence doing internal innovation as well?

A: We're going to take a very balanced approach with acquisitions and internal innovation. We are going to continue to do acquisitions, but we will also continue to build upon our innovation culture. We will do a lot of internal innovation and we will continue to attract a lot of top talent to our four business groups.

Every acquisition we make is done very thoughtfully. We acquired Denali because memory is more and more of a bottleneck, and memory IP is very critical for us. Tensilica is a very good acquisition for us because it brings us deeper into the mobile space where we can support such developments as LTE, multimedia, and video. Sigrity has tremendous importance for PCB in analysis-sensitive markets such as high-end consumer and data center infrastructure. We bought Azuro for its clock tree synthesis and optimization, and it's been a huge help in digital implementation.

Q: Some acquisitions go well, and some go poorly. Cadence acquisitions seem to be working. What makes the difference?

A: We consider every acquisition very carefully. For example, I've been watching Tensilica for three years, and I like the team and its talent. They have 200 people and we want to make sure they stay with us and have the opportunity to make a broader impact.

We also hold ourselves accountable. Every quarter we look at whether the acquisitions are working for us, and whether the synergies we talked about are happening. We provide transparency to our shareholders so they know what we are doing.

Q: What are the priorities for the four business groups Cadence now has?

A: We have combined our advanced functional verification and hardware-assisted verification assets together under one group. This enables us to focus and provide optimized, complete verification solutions for our customers, including hardware /software co-design and co-verification solutions for our systems customers. There is a lot of growth potential in the System and Verification Group.

Custom/analog is a stronghold for us, and we will continue to drive even more automation. You saw our recent electrically aware design announcement, where we can give real-time electrical feedback to the circuit designer. PCB is very much related to this area because it includes custom ICs, RF, and IC packaging. We will drive further growth in the PCB space through our Sigrity acquisition.

The next group is Digital and Signoff. We see signoff as a big market. The incumbent signoff provider is very strong, but we found the best team and we rewrote our timing signoff tool [Tempus] to support up to 100 CPUs. We are also driving innovation in place and route and synthesis.

Lastly, we built our IP offering from scratch, and now we are number four in the IP space. We will continue to grow that IP business because IP reuse is becoming more and more important, and customers want to outsource IP through a reliable partner. Our key to success is to maintain quality and provide differentiating IP, not the commodity IP that everybody can do.

Q: You have talked about "doubling down" in verification. What's driving that and how is Cadence responding?

A: As chips become more and more complex, verification is really the key bottleneck for a lot of our customers. We provide an advanced functional verification solution with our Incisive platform. We also have our Palladium hardware emulation platform. I believe Palladium will continue to grow as there is a growing adoption of hardware-assisted verification. We are clearly the leader [in emulation], and we are putting a lot of R&D into the next-generation product so we can offer better performance, lower power, and more scalability.

We also have a couple of initiatives driving to higher level of abstraction, like C-to-Silicon Compiler in high-level synthesis, and for embedded software development through virtual platforms. Clearly there is a high potential for growth, so we are continuing to pursue innovation and R&D in this space.

Part two of our conversation with Lip-bu Tan, focusing on EDA challenges and opportunities, is on the Fuller View blog.

Richard Goering



By Craig Wolverton on August 29, 2013
As a former employee with fond memories of Cadence, I am glad to read about some of the changes detailed here. Combining functional verification and hardware-assisted verification under one group at this point in time makes more sense than ever as long as it results in the synergy that should come from it. One aspect should not overshadow the other and a sense of trust for the common good should be encouraged and rewarded.

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