Home > Community > Blogs > Industry Insights > memcon 2013 keynote panel and session proceedings available
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

MemCon 2013—Keynote, Panel, and Session Proceedings Available

Comments(0)Filed under: Industry Insights, memory, DDR, DRAM, MemCon, flash, Cadence, memory IP, DDR4, hybrid memory cube, LPDDR4, memory conference, MemCon 2013, LPDDR, semiconductor memory, SoC: memory interfaces

The MemCon 2013 conference, held August 6 in Santa Clara, California, provided a comprehensive overview of the past, present, and future of semiconductor memory technology. Nearly 500 attendees came to hear three keynote speeches, an expert panel, and three tracks of technical sessions. Whether you attended or not, you can now download presentations from the MemCon proceedings web page.

Presentations are available for the following events:

MemCon Keynotes

Memory: A Key System Optimization Challenge—Martin Lund, Cadence
Hybrid Memory Cube: Your New Standard for Memory Performance—Mike Black, Micron
New Directions in Memory Architecture—Bob Brennan, Samsung

MemCon Panel

Wider vs. Faster—Jim Handy, Objective Analysis, moderates a panel session including Shafy Eltoukhy (Open-Silicon), Becky Loop (Intel), Bill Gervasi (Discobolus Designs), and Gopal Raghavan (Cadence).

MemCon Track 1—DRAM

Successful Probing of DDR4 and LPDDRR3/4 for Functional Validation and Debug—Jennie Grosslight, Agilent
LPDDR4: Evolution for a New Mobile World—JY Choi, Samsung
Tuning DDR4 for Power and Performance—Mike Micheletti, Teledyne LeCroy
SoC Memory Interfaces, Today and Tomorrow at TSMC—Lilius Paris, TSMC

MemCon Track 2Memory Subsystems

Test Implications for SoC Designs Utilizing LPDDR—Prashanth Thota, Tektronix
Embedded Resistors for High Performance Memory Solutions—Bill Gervasi, Discobolos Designs
Flash Storage Solutions for Embedded ApplicationsMaking the Right Choice—Victor Tsai, SMART Modular Technologies.
Designing for DDR4Power and Performance—Trung Tran, Altera

MemCon Track 3Emerging Technologies

Memory Scaling: A Systems Architecture Perspective—Onur Mutlu, Carnegie Mellon University
Applications and Advantages of Low Power ReRAM—Lee Cleveland, 4DS
High Performance Memory Opportunities in 2.5D Network Flow Processors—Jay Seaton, Netronome
True 3D Memory Architecture Yields Amazing Performance—David Chapman, Tezzaron Semiconductor

Again, you can access these presentations at the MemCon 2013 proceedings web page. No registration is required.

Richard Goering

Cadence Blogs About MemCon 2013

Wide I/O 2, Hybrid Memory Cube (HMC) - Memory Models Advance 3D-IC Standards

Semiconductor Memory Challenges Will be Overcome, MemCon Keynoter Says

Scaling the Semiconductor Memory Wall

MemCon Samsung Keynote: New DRAM and Flash Memory Architectures are Needed

MemCon Panel: Promises and Perils of 3D-IC Memory Standards

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.