EDA analyst Gary Smith (right) has been advocating electronic system-level (ESL) design since 1997, and he has just declared that the industry finally has a "true" ESL flow. In an archived August 19 webinar, Smith and three ESL experts—including two from Cadence—discuss what today's ESL flow can accomplish and where we can go from here.
The webinar is titled "ESL—Are You Ready?" It opens with a presentation in which Smith shows how the ESL flow has evolved since 2011, when it first started to come together. This presentation is followed by a discussion that includes:
- Mike Gianfagna, vice president of corporate marketing, Atrenta (and moderator of the webinar)
- Jason Andrews, architect, Cadence
- Frank Schirrmeister, group director, product marketing, Cadence
A fourth participant is Alberto Sangiovanni-Vincentelli, who happened to be in the audience. A long-time advocate of system-level design, he's a professor at the University of California at Berkeley and a member of the Cadence board of directors.
Smith's declaration does not mean that system-level design is a completely solved problem. The new ESL flow, he said, is "done with chewing gum and bailing wire and all sorts of things to get it to work. It's not an elegant flow but it is a working flow."
Piecing the flow together
Smith first reviewed the 2011 ESL flow. It included four abstraction levels of software virtual prototypes, and the top level was called the Architect's Workbench. (For further information about these four types of software virtual prototypes, see this Frank Schirrmeister blog post). The flow also included ESL design entry. There was no silicon virtual prototype, only spreadsheets. And the flow from the architect to both hardware and software development was broken.
In 2012, Smith said, Atrenta released a silicon virtual prototype. Gianfagna noted that Atrenta uses different terminology, but the goal is the same—an RTL signoff flow with a complete analysis of "all the dimensions that matter," including test, power, timing, and physical routing.
But there was still another problem in 2012—power information wasn't getting "anywhere close" to the system architect. The silicon virtual prototyping engineer would find that the design wasn't going to meet the power budget, and he or she would start adding accelerators, GPUs, and other features to meet the power budget. "The good news is that it worked. The bad news is that now the model the architects passed to the software engineers was wrong," Smith said.
The software developers didn't have a place to start, and they found they really needed hardware tools such as emulators, accelerators, and rapid prototyping. This gave them accurate models, but now they had to develop hypervisors and schedulers for multi-core systems. The net result is a complicated flow that includes two levels of the silicon virtual prototype, three levels of the software virtual prototype, and emulation and hardware prototyping.
Smith went on to identify the main ESL flow players, and to identify "heroes" of both RTL design and ESL design. Among his ESL heroes is Sangiovanni-Vincentelli, who Smith said was right about platform-based design in 1996 or 1997. "It took a long time to convince me, but he was right on." Smith also included Gianfagna, Andrews, and Schirrmeister in his ESL "heroes" list.
Here are some takeaways from the discussion that followed.
Different abstraction levels are needed
Schirrmeister: In 1997, when I came to the U.S. and we worked with Alberto on Felix [Cadence project], we thought everything would happen in the virtual prototype and we would be able to abstract everything. The reality is that you need to refine and confirm, and some decisions bounce back and forth between lower and higher levels.
Gianfagna: The interesting question is where you stop. How much software can you run in this model today and is it enough? Will it be good enough or do we need even higher speed models?
Schirrmeister: The problem is that verification is completely unbounded. It will never be done.
Gianfagna: Yeah, you're done when you're out of time.
Schirrmeister: We see people making the boot-up of Android or Linux a requirement for tapeout. They can do that using emulation and FPGA-based prototyping and so forth. Then the interesting trend is that people are combining the different engines, using virtual models together with some hardware models.
What types of software are in the ESL flow?
Schirrmeister: Jason, can you comment on what types of software you're seeing? Is it everything from drivers to lower stages of the middleware?
Andrews: That's right, it's everything from the bottom up to the initial applications to see if the whole stack is functioning. What I see as the biggest challenge is how to use the flow with the time you have. There are a lot of choices on where you can apply effort and it's not easy to find exactly the amount of time to spend at each place.
A "dream" silicon virtual prototype
Gianfagna: Today, at the silicon virtual prototype level, we have a very high degree of visibility from the RTL forward. We know if there's going to be routing congestion, and we know what the timing constraints are. But are we confident we're building the right chip for the end application? Maybe not. The dream I have is to build a silicon virtual prototype and bring that up to the software world, where the application becomes the living specification.
Sangiovanni-Vincentelli: You talked about the application code being the ultimate specification. That's a functional specification, if you like. But there are other non-functional specifications like power, timing, size, and cost, and all these have to be estimated in parallel. We are spending a great deal of time right now in research about requirement specifications. There are different classes of requirements you need to think about, especially if you're going to do some formal analysis.
Is there ESL for analog?
Schirrmeister: We have an on-line comment that the ESL flow appears tailored for digital. What about analog or RF? Yes, the software piece is probably first adopted by the digital side. But what we see today, with the Internet of Things, is a requirement to bring in more analog/mixed-signal pieces. We see software executing and connecting to real number models in Verilog. There will be more and more dependency on the analog/mixed-signal side going forward.
Gianfagna: We don't do analog analysis, but at the analog/digital interface a lot of things go wrong, and there are opportunities for us in that.
Gary Smith's parting remarks
"First, I'm not looking for the magic green button from silicon compiler days. You can't push a button and have everything work. Secondly, vendors should never advertise that they have a single cycle tool. The engineer always wants to touch the design one more time. Make sure you don't take the engineer out the equation. He has to be there to drive the tool."
Note: The archived webinar is available at the Atrenta web site. Frank Schirrmeister has a blog about the webinar at the Chip Design Magazine SLD community site.
Related blog posts
Getting Ready for ESL with Emulation!
Gary Smith at DAC 2013—the $170M SoC Design is a "Myth"