Home > Community > Blogs > Industry Insights > memcon samsung keynote new dram and flash memory architectures are needed
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

MemCon Samsung Keynote: New DRAM and Flash Memory Architectures are Needed

Comments(0)Filed under: 3D, memory, DRAM, MemCon, flash, MRAM, 3D-IC, Samsung, storage, wide i/o, PCI Express, NAND flash, PCIe, SSDs, HDDs, latency, bandwidth, data centers, hybrid memory cube, HMC, Samsung keynote, hard disk drives, tiering, MemCon 2013, tiered memory, 3D vertical NAND flash, Bob Brennan, tiers, MemCon keynote, capacity, STT-MRAM

Want to know what Samsung is thinking about the future of DRAM and NAND Flash memory technology? That all became clear at an informative and entertaining keynote speech at the MemCon conference August 6, 2013, where Bob Brennan, senior vice president of the Memory System Architecture Lab at Samsung Semiconductor, spoke about "New Directions in Memory Architecture."

Brennan first discussed the challenges of DRAM bandwidth and capacity scaling, and suggested that part of the solution for mobile devices is the adoption of 3D architectures with the JEDEC Wide I/O standard (the latest is Wide I/O 2, as described in this blog post). The other part of the solution is a transition to "tiered" memory architectures.

Brennan went on to discuss NAND Flash capacity scaling, endurance, and bandwidth, and predicted that data centers will increasingly switch from hard disk drives to NAND Flash. Finally, he presented STT-MRAM (magnetoresistive random access memory) as a technology with "persistent performance" that gets close to the capabilities of DRAM.

While it received only a brief mention in Brennan's speech, Samsung announced August 6 that it has started to mass produce the industry's first 3D vertical NAND Flash. Aimed at a wide range of consumer and enterprise applications, the 3D V-NAND technology offers 128 Gbit density in a single chip. This development echoes Brennan's statement that it's very difficult to scale NAND Flash capacity using planar technology, and consequently "you have to go 3D in some way or form."

Can DRAM Keep Up?

DRAM, Brennan said, is facing "fundamental challenges" in scaling for bandwidth and capacity. As servers add more and more processor cores, demands for capacity are, in some cases, increasing exponentially. At the same time, mobile devices such as the Samsung Galaxy S4 demand high bandwidth in a tiny form factor. Finally, latency has remained constant in recent years, and designers are compensating with increasingly sophisticated caching structures.

So what to do? One solution is to "go wide" for bandwidth, and with a 512-bit wide interface to memory, Wide I/O certainly accomplishes that. "In the mobile space, I think Wide I/O 2 with a tiered memory structure is going to be the way to go," Brennan said. Another 3D technology, the Hybrid Memory Cube, is aimed at enterprise applications.

However, Brennan noted, these two technologies don't change the semiconductor physics of the DRAM, they just organize it differently. They provide good bandwidth and low latency, but how do you get the capacity? "What I would propose to the industry is that we need a new memory architecture to solve these problems," Brennan said.

Stacking is very difficult, he noted, and in mobile applications, Wide I/O may initially be coupled with LPDDR4 technology. And that brings in tiering. "Suddenly you don't have a monolithic memory any more," Brennan said. "You have a very high-bandwidth memory, and then there's a higher capacity memory that's further from your processor." Likewise, in the server space, there will be a tiered structure with a high-bandwidth memory close to the CPU.

There are different ways to organize high-bandwidth and high-capacity tiers, but "I would submit we must move here as an industry and relatively soon," Brennan said.

Scaling NAND Flash - Performance, Endurance, Capacity

To scale NAND Flash capacity, Brennan argued, a 3D approach is needed. But endurance is also a tough challenge, and it becomes more and more difficult as process nodes shrink. Designers have compensated by putting more sophistication into controllers. This requires algorithms that are tuned for the semiconductor process.

Standard interfaces are helping with NAND Flash performance. "PCIe [PCI Express] is ubiquitous and it really unlocks the bandwidth," Brennan said. "It gives us the necessary bandwidth, and it connects the Flash directly to the bus that feeds into the CPU hierarchy. It reduces the latency for Flash." The challenge now is keeping up with the maximum data rates that will be allowed by future standards.

Eventually, Brennan said, NAND Flash will become intelligent enough that we'll have to re-examine how we balance the storage workload. Today, he noted, many people are using NAND Flash as a read/write cache in front of storage. "I think this trend will continue and there will be more and more Flash in the data center. Flash will get faster and faster. So I see the enterprise pretty much transitioning to Flash."

In the future, he said, an intelligent flash "tier" will provide just enough flash for a given application, and that will determine dollars per IOPS and per gigabyte. This will help spark a transition away from hard disk drives.

STT-MRAM - A New Alternative

Hard disk drives and NAND Flash devices have high latency and relatively low bandwidth. DRAM has lower latency and higher bandwidth. There's a space in the middle of this spectrum, Brennan said, for what he calls "persistent performance." And that's where STT-MRAM comes in.

"Persistent performance is memory that gets close to the behavior of DRAM, but it has the characteristic of Flash in that it is persistent," he said. "That's the space we're looking at next." MRAM requires a new cell structure, but it has "very good characteristics" in terms of standby power and retention, Brennan said. Speed is getting close to, if not exceeding, DRAM technology. Cost per bit will initially be high but will come down as production ramps up.

"The technology is not very mature at this point, but we think there's a lot of potential," Brennan said. "It leads to memory architectures that have new possibilities."

Brennan's presentation is available at the MemCon proceedings web site.

In the following video clip, Sean O'Kane of ChipEstimate.com TV interviews Brennan. The discussion includes Samsung's high-performance, non-volatile memory (NVM) technology; the challenges of capacity scaling; and Samsung's "green" philosophy in both its semiconductor development and its new Silicon Valley building.

Richard Goering

Related Blog Posts

Semiconductor Memory Challenges Will Be Overcome, MemCon Keynoter Says

Wide I/O 2, Hybrid Memory Cube (HMC) - Memory Models Advance 3D-IC Standards

An Update on the JEDEC Wide I/O Standard for 3D-ICs

Wide I/O Memory and 3D ICs - A New Dimension for Mobile Devices



Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.