The term "paradigm shift" is overused, but I think it just might apply to the Virtuoso Layout Suite for Electrically Aware Design (EAD) product announced by Cadence today (July 10, 2013). Behind this product is a new methodology that provides in-design, real-time interconnect parasitic extraction and analysis that verifies whether the layout is electrically correct as it is being constructed.
The EAD approach has several immediate benefits, including the following:
- Layout designers receive immediate feedback on how a layout feature or change will impact design requirements - as they draw the layout.
- Layout designers can discover electromigration issues as they're drawing the layout, and avoid problems immediately instead of waiting for a post-layout extraction.
- Circuit designers can run "partial layout resimulation" to ensure that interconnect parasitics are not harming circuit performance.
- Circuit designers can set electrical constraints (like matched resistance or capacitance) and pass these along to layout designers, who will receive instant feedback on whether the constraints are being met.
What makes it all work is an in-design parasitic extraction engine that has been integrated into the Virtuoso Layout Suite. While not intended for signoff, it's a highly accurate, 2.5D extraction engine that runs in real-time as layouts are drawn. It extracts resistance, capacitance, and coupling capacitance without requiring an LVS or DRC-clean layout. Most importantly, the engine offers real-time, incremental, net-by-net extraction.
You may remember that Cadence introduced a technology called "partial layout" with the Virtuoso Advanced Node release in January 2013 (blog post here). That technology allows designers to extract device parameters before an LVS/DRC clean layout is constructed. Its purpose is to provide early insight into layout-dependent effects (LDE). The "partial layout resimulation" capability in EAD uses the same flow, but focuses on interconnect parasitics instead of LDE device parameters.
The Long Wait
At any process node, interconnect parasitics can have a profound impact on circuit performance and power. Until EAD, "the only way to understand the impact of interconnect parasitics was to have a completed layout," said David White, R&D group director at Cadence. "That layout had to have all of the devices in the layout view, it required all of the interconnect be complete, and it had to pass LVS." Only then could designers run extraction and pull out interconnect parasitics, and map them into a new netlist for simulation-enabled analysis.
The diagram below depicts some of the problems with today's custom/analog flow. Since extraction cannot be run until layout is complete, layout designers have little insight into how physical design decisions will impact electrical characteristics. Multiple design iterations are often required to achieve successful silicon.
So how do custom/analog designers work around this bottleneck today? "They overdesign circuits to meet the increasingly complex reliability and EM requirements," White said. "The problem with overdesign is that it's going to cost them area and it's going to cost them power." To mitigate electromigration, designers simply widen wires to avoid current density problems. In addition to taking up more area, the wider wires result in increased capacitance.
The EAD flow, in contrast, provides continual electrical checking and verification between circuit and layout design. Circuit designers can pass electrical constraints to layout designers. Circuit designers can re-simulate using extracted parasitics from partial layouts to ensure design intent is met throughout physical design. Layout designers will know instantly if they draw something that doesn't meet constraints. Layout designers can also discover electromigration problems as interconnect is created, rather than leaving them buried in the circuit to deal with at the end. This results in better communication of design intent, faster resolution of possible problems, and no need for overdesign.
EAD is applicable to all process nodes. "It's for any custom or analog design where uncertainty associated with interconnect parasitics can influence circuit performance, or electromigration issues are present," White said.
Circuit and Layout Designers
EAD gives circuit designers the ability to set meaningful electrical constraints. The Cadence Virtuoso environment has long been constraint-driven, but before EAD only physical constraints were really practical - you could set an electrical constraint like maximum resistance, but it could only be met through a post-layout extraction. With EAD, circuit designers can set electrical constraints using the Virtuoso Circuit Prospector and the Constraint Management System, just as they set physical constraints today - and layout designers will know right away if they draw a feature that violates those constraints.
There's another benefit for circuit designers, White noted. "The tool is creating data that the circuit designers would love to have, and that is the parasitic information as the layout is being created. The circuit designers could literally resimulate their circuit for each new critical net that's added." If there's a problem, he noted, debugging will be much simpler and there are more options for alternative solutions.
The EAD flow also promotes collaboration by providing a unified electrical view between Virtuoso ADE and Virtuoso Layout. Gone are the days of communication through manual annotation of currents, and the resulting transcription errors. White noted, "The circuit and layout designers can literally optimize some part of the layout and quickly view the resimulation results in ADE to maximize performance, and verify there are no EM violations in layout. All the parasitic and simulation data are seamlessly transferred in the background."
Virtuoso Layout Suite EAD is first and foremost a tool for layout designers. It provides several ways to notify layout designers if they're violating a constraint. The tool will place a red flag on the layout if a constraint is violated. A virtual "ohmmeter" can be placed on any two points on a wire, and it will show how much current passes through those points. There's also an "info balloon" that will provide information about resistance and capacitance values, as well as maximum current carrying capability, as the designer draws.
The electromigration (EM) analysis, White said, requires no design style changes. The current on the interconnect is already known from Virtuoso ADE-XL simulation. The EM solver takes the extracted data along with the simulation data, and determines whether a given line can manage the amount of current that's going through it. Color coding gives the layout designer feedback - green is good, red indicates a problem (right). The tool also gives hints on how to fix the problem.
The EM analysis works throughout the metal stack and also understands multi-cut vias. Designers can move from the cell level to the block level and the chip level, and be correct-by-construction with respect to EM issues throughout the hierarchy.
So where is all this heading? The long-range vision is that electrically aware design will eventually turn into electrically driven design, which will use automated constraint generation to drive placement and routing. So stay tuned - innovation in custom/analog design is accelerating.
Here are two resources that provide more information about electrically aware design as a methodology:
EE Times article, Electrically-aware design improves analog/mixed-signal productivity
Chapter 9 in Mixed-Signal Methodology Guide published by Cadence in 2012
To learn more about the Virtuoso Layout Suite for Electrically Aware Design product, click here. To view a short video presentation by David White, click here.