At 28nm and below, the performance of a device can vary greatly depending on what it is placed near in the layout. For this reason, layout-dependent effect (LDE) is one of the most challenging aspects of advanced node design. A recently archived webinar shows how TSMC and Cadence worked together to develop a LDE-aware custom/analog design flow.
The TSMC-Cadence webinar is titled "Variation-Aware Design: Detecting and Fixing Layout-Dependent Effects Using the Cadence® Virtuoso® Platform, Part II." It is a sequel to Variation-Aware Design, Part I, an earlier webinar that provided a basic introduction to LDE and showed how the Virtuoso platform can help mitigate these effects. Speakers in the "Part II" webinar include:
- Jason Chen, design methodology and service marketing, TSMC
- Manoj Chacko, DFM product management, Cadence
- Bala Kasthuri, DFM product management, Cadence
The fundamental problem is that transistor device characteristics vary depending on the context, placement, and density of neighboring transistors. The LDE impacts the electrical performance of the transistors. In the example shown at the right, the well proximity effect (WPE) increases the chances of a mismatch in a differential pair.
Collaboration Provides LDE Solution
In the webinar, Chen provided an introduction to LDE and then discussed LDE-API, an innovative solution developed through collaboration between Cadence and TSMC. This collaboration was made possible through the TSMC Open Innovation Platform (OIP). Chen also provided an overview of the TSMC 20nm reference flow.
Chen noted that LDE is related to layout placement and silicon stress, and is driven by such factors as proximity to well edges, isolation, and active regions. LDE directly impacts electrical characteristics such as Vth and Idsat. Different layouts based on the same schematic can result in more than a 20% difference between pre-simulation and post-simulation results. Thus, both circuit designers and layout designers need to account for LDE as early as possible.
Chen described four key LDE parameters:
- Well Proximity Effect (WPE) - the closer to a well edge, the higher the threshold voltage variation
- Poly Spacing/Length Effect (PSE, PLE) - spacing and length of polysilicon dummy gates impacts the drain current
- Length of Diffusion (LOD) - caused mostly by silicon stress resulting from shallow trench isolation (STI), LOD results in device variability
- Oxide Spacing Effect (OSE) - neighboring STI stress affects device uniformity
Chen showed how TSMC and Cadence jointly developed an LDE-aware custom design flow to mitigate these effects. The flow lets circuit and layout designers run LDE-aware re-simulation using device parameters from partial or completed layout. It reduces design iterations and helps designers analyze LDE impacts to electrical performance. The flow has been validated in TSMC 28nm and 20nm processes.
The flow is made possible by the TSMC LDE-API, which provides a direct link to the Cadence Litho Electrical Analyzer. LDE-API translates LDE physical layout dimensions into netlist in-line model parameters that are understood by the circuit simulator. LDE-API is built into the process development kit (PDK) and it links the transistor LDE properties into the Component Description Format (CDF).
"It is clear that LDE-API is playing an important role in the new custom design flow," Chen concluded.
LDE-Aware Flows in Virtuoso
In the second part of the webinar, Manoj Chacko showed how the Cadence Virtuoso platform offers LDE-aware flows for circuit designers and layout designers. For circuit designers, Virtuoso can extract the LDE parameters from a partial or complete layout and run a re-simulation. For layout engineers, Virtuoso supports a what-if LDE analysis that can help the engineer understand the impact of LDE on different placements.
Chacko noted that the circuit designer needs to understand the impact of LDE early on, as he or she is building the circuit. What's needed is a prototype layout that can bring accurate parameters back into simulation. Virtuoso makes this possible in two ways - re-simulation with Modgen (Module Generator) constraints, in which case no layout is needed, or re-simulation with a partial placement and layout. The LDE-aware flow is depicted below.
For the layout engineer, Virtuoso can provide information about LDE early in the layout process so placement can be easily modified. Thus, problems can be fixed before DRC, LVS, and extraction. Chacko noted that post-layout SPICE is too late to identify the LDE impact on layout.
"Because of the integration with TSMC LDE-API, designers can find out which transistors have characteristics that are different from what was intended," Chacko said.
The webinar closed with a demo run by Bala Kasthuri of Cadence. To view the webinar, click here. A Cadence log-in is required. If you don't have one, you can register here.
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