One of the best things about the Design Automation Conference (DAC) is the ability to hear about design challenges and solutions from other engineers. And one of the best places to do so at the recent DAC 2013 was the Cadence Theater, which featured three full days of customer and partner presentations. Most of these presentations are now available in the form of audio tapes and slides at the Cadence DAC microsite.
Here's your chance to learn from engineers at companies like Freescale, AMD, Broadcom, Texas Instruments, Marvell, Siemens, NXP, and many others. Most of the presentations are 20-30 minutes in length. I attended several and found that most drew standing-room-only crowds, like the session depicted below.
The Tensilica presentation at the Cadence Theater attracted a big crowd of listeners.
I blogged earlier about the Evatronix presentation at the Cadence Theater (held just before Cadence completed its acquisition of Evatronix' IP portfolio). Jack Erickson recently blogged about a very interesting joint presentation including Cadence and high-level synthesis competitor Forte Design Systems.
Audio recordings and slides are available for the following presentations. To access these presentations, click here.
Monday June 3 Presentations
Implementation of a Multi-Threaded 64-bit Power Architecture Core on the RPP, FPGA-Based Prototyping System
Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
Best Practices in Verification Planning
Contemporary Verification Consultants
Objective Measure of Verification Quality with IEEE 1647 (e) and Incisive HAL
Complementing In-Circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity, and Performance
Faster System Bring-Up with an Embedded Testbench on Palladium
Implementing Power Gating Flow with CPF
Statistical Characterization Approach Using Liberate MX with 40nm Low-Voltage SRAM
Innovating Together to Build Exceptional PDKs
Tuesday June 4 Presentations
Substrate Noise Isolation Extraction/Model Based on Foundry Measurement Using Cadence Analog Flow
Power-Mode Verification in Mixed-Signal Chips
Highly Scalable Multicore ARM A15 Verification with Specman/e.
Forte and Cadence
How to Broadly Deploy SystemC High-Level Synthesis for Production Hardware Design
SoC Interconnect Analysis for Effective Verification, Architectural Exploration, and Post-Silicon Debug
Towards Formally Proven Embedded System Design with an Unambiguous HW/SW Contract
Customizable Processor Basics
Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis
Musings on Advanced Functional Verification with Specman/e in FPGA for Medical Devices
Layout Dependent Effects—Exploring LDE Analyzer
Wednesday June 5 Presentations
A Roadmap for DFM and Physical Design at the Limits of IC Scaling
Must-Have IP for Your SoC: NAND Flash, SlimBus, and USB Controllers
The Best of Both Worlds—Combining Virtual and FPGA-based Prototypes
20nm/14nm Analog and Mixed-Signal Flow
Ubiquitous PCI Express Verification from Simulation Through Post-Silicon Development
SMIC—Your Foundry Partner for Success in China
Efficient PHY Test Approaches for PCIe Gen3 Compliance and L1 Sub-State Verification
Hardware Solutions for FPGA-Based Prototyping
Cadence and AMD
UVM Multi-Language with e, SystemVerilog, SystemC, C/C++
Firmware Development and Pre-Silicon Verification with FPGA-Based Prototyping
Again, click here to access the presentations. Enjoy!