Bill Dally, chief scientist at NVidia, thinks that two engineers in a garage should be able to design a prototype system on chip (SoC) in a couple of weeks. At the recent Design Automation Conference (DAC 2013), he presented a plan for making that possible—a modular chip design strategy that leverages much larger building blocks than standard cells.
Dally, who is also a professor of electrical engineering and computer science at Stanford University, gave a "short keynote" (called a SKY talk) at DAC June 5. The talk was titled "21st Century Digital Design Tools," and Dally set forth some of the requirements for such tools.
At the start of his fast-moving talk, Dally reminisced about starting a company in the 1980s while he was a graduate student at Cal Tech. He and his co-founders designed a full custom chip in a couple of weeks. "It was an era of innovation in which a few guys in a garage could build something," he said. "And since then I've noticed a steady downward progression in what a couple of guys in a garage can do. I think this is a really awful thing."
Dally said that it is "just scandalous" that SoC design takes as long as it does. "We have a productivity crisis in digital design," he said. "If I want to design an SoC with no new IP—all pieces I have used before—it still takes months and a huge amount of physical labor to do the physical design of an SoC."
So why do we care? Dally noted that it may take $50 million to bring a "relatively simple SoC" to its first lab prototype, and possibly $100 million to start shipping a product. Venture capitalists aren't willing to provide that much funding. As a result, there are fewer fabless semiconductor startups and there is less innovation.
"I would argue that you can design a system in a few days, using existing IP," Dally said. "There is an existence proof for this—it's a printed circuit board." He noted that it's possible to design a complex PCB in a few days and get a prototype back in less than a week. With a PCB, the IP consists of packaged ICs and devices, and the PCB designer can't go in and change the IP.
The problem with contemporary SoC design flows, Dally said, is their failure to preserve abstraction. There are two aspects to abstraction—modularity and information hiding. Today's tools, he said, "encourage pushing everything down to gates and trying to handle billion-gate designs flat. This breaks previously working modules. I can take a processor that's worked many times before, plop it into a new design, and the timing doesn't close." With RTL as a starting point, he noted, "we are basically redesigning the processor every time we touch it."
Stop Oozing Logic
Information is hidden at the PCB level because the designer can't look inside the packages. IC designers, however, can look inside modules, and they frequently make changes in attempts to squeeze out a little more performance. Designers break into the modules, "let RTL ooze in weird blobs," and then try to close timing, a futile exercise because all structure in the design has been destroyed. "Oozing logic," said Dally, "is harmful."
So how should chips be designed? In Dally's view, the ideal design flow would rely on hard IP blocks and be much like a PCB design flow. It would include these elements:
- Hard IP in fixed-height modules to simplify the chip assembly process. "I don't want an ARM core in RTL, I want a Cortex-A9 in TSMC 16nm FinFET technology provided as a 1mm high module."
- Fixed heights should be around 0.5-2.0mm so that for very large chips, there won't be more than 1,000 modules.
- All IP should conform to a standard network-on-chip (NoC) interface so everything plugs into everything else.
- I/O should be captive so modules can be self-contained units.
- No route-throughs—"We don't want later changes in the design to disrupt what's inside a block."
It may sound radical, but as Dally said, "what I'm suggesting here is just up-leveling standard cells to modern sizes. Rather than a standard cell about one micron high, I'm suggesting modules on the order of 1mm high, so they are 1,000 times larger in both directions. That's the right level at which to be composing our chips."
As a result, designers will build chips using hundreds of modules, not billions of cells. Placement will become "trivial" because the designer is using hierarchy to solve the placement problem. Designers will close timing for a module once and never have to worry about it at the top level. At least that's the theory.
The hard part (no pun intended) in all this is coming up with the IP, and Dally recognizes that. "What is standing between us and designing a really great SoC in a few days is lack of an ecosystem," he said. The most critical part of that ecosystem is the IP, and it is "easily 90%" of the ecosystem. Module placement and assembly, on the other hand, is "trivial."
But suppose the IP challenge could be overcome. A designer could create an SoC in a few days, and get to a first prototype not after $50 million but with $5 million or perhaps even $500,000, Dally said. This takes us back to that earlier era of garage-scale innovation. "A couple of guys in a garage could still turn out a really great chip and change the world with it."
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