With the recent release of the IEEE 1801-2013 (UPF 2.1) power intent format standard, prospects for "methodology convergence" between the Unified Power Format (UPF) and Common Power Format (CPF) are looking good. One company that has used both formats and is following the evolution of power standards is STMicroelectronics.
Fellow Cadence blogger Adam Sherer and I recently spoke with David Vincenzoni, who works in the Industrial and Power Conversion Division of STMicroelectronics. His group develops large, complex industrial ASICs with embedded processors, including mixed-signal ASICs and SoC power line modems. Low power design is key, and many chips have two, three, or more power domains that can be switched on or off or carry different power levels. "It is vital to have a proven, low-power flow that goes from RTL to signoff," Vincenzoni said.
According to Vincenzoni, key challenges in low-power design include the following:
- Designers need to anticipate bad connections that could occur during RTL design. "This means that we have to simulate the power domains in the RTL using the power description that will be used in the next steps of the implementation phase."
- The need for a language that can describe high-level power intent at the RTL stage, and also has the constructs to describe power intent at the physical level.
- Developing formal checks between the power-off and isolation cells.
The last SoC developed by Vincenzoni's group had two power domains with three power modes. There were also several level shifters between the core logic and the I/Os. A separate power domain was represented by an analog front end. Engineers used CPF for verification and UPF for implementation, and also used equivalence checking for the power intent.
Using IEEE 1801 UPF
For a recent IP development, Vincenzoni's group used IEEE 1801 UPF along with verification from the Cadence Incisive simulator. The block has two power domains and three possible power modes. A block diagram of the IP block is below.
Vincenzoni explained: "Through Specman and the UPF 1801 description of the power intent, we simulated the power modes of this IP. The implementation engineer used the same UPF 1801 description during the synthesis and equivalence checks. This IP can be delivered with the UPF 1801 description file, which can be included with the power intent of the SoC that will integrate it."
According to Vincenzoni, the older Accellera UPF 1.0 standard could be good enough for a power intent description at the implementation level, but it is too detailed for an RTL description. IEEE 1801-2013, on the other hand, inherits several CPF constructs that allow a high-level description of the power modes of the design, and it also supports low-level descriptions for the back-end flow.
Advice for UPF Users
By leveraging CPF constructs and deprecating some of the older UPF 1.0 commands, IEEE 1801-2013 opens the door to methodology convergence between UPF and CPF. Power format convergence is the "right way," Vincenzoni said. "For the designers, it is essential to have a language that is supported by all the tools of the ASIC design flow."
At present, STMicroelectronics uses the IEEE 1801-2009 (UPF 2.0) standard, and expects to stick with that through the next few projects. Vincenzoni said his group is "interested" in IEEE 1801-2013 but has to take tool support into account.
Vincenzoni's advice to UPF users: "Start to use UPF 1801-2009 and follow the evolution of the standard. Start now with UPF 2.0, and when the tools support UPF 2.1 it will be easy to switch."
Related Blog Post
A CPF User Perspective on IEEE 1801 (UPF) "Methodology Convergence"