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DAC 2013: Accellera Panel Updates Power Format Standards

Comments(0)Filed under: Industry Insights, DAC, low power, OSCI, UPF, Si2, CPF, Accellera, IEEE, Spirit, Krolikoski, Rawat, power standards, IEEE 1801, Qi Wang, DAC panel, power formats, Biggs, 1801-2013, DAC 2013

In what was billed as a "town hall meeting" about the new IEEE 1801-2013 (UPF 2.1) power intent format standard, the Accellera Systems Initiative sponsored a breakfast panel at the Design Automation Conference (DAC 2013) Monday, June 3. The discussion took a broader look at power intent formats, how they're used, and where they're headed.

At the beginning of the meeting, EDA standards veteran Stan Krolikoski -- distinguished engineer at Cadence -- received the annual Accellera Leadership Award. Krolikoski was a co-founder of Accellera in 2000, and today he serves on the board and heads the IP Rights Policy committee. Accellera chair Sishpal Rawat (right in photo) noted Krolikoski's long involvement with Accellera, the Open SystemC Initiative (OSCI), the Spirit Consortium, and the IEEE, where he serves as chair of the IEEE Design Automation Standards Committee (DASC).

Accepting the award, Krolikoski observed that "I really think we need a new generation of standards leaders to come forward. We're seeing a few people, but we're not seeing enough."

The panel was moderated by Ed Sperling of System-Level Design. The panelists had participated in an IEEE 1801-2013 tutorial held the day before. Panelists were as follows, shown left to right below:

  • Jeffrey Lee, Staff Corporate Application Engineer, Synopsys
  • Qi Wang, Solutions Group Director, Cadence
  • Sushma Honnavara-Prasad, Principal Engineer, Broadcom
  • John Biggs, Senior Principal Engineer, ARM (and chair of IEEE 1801 Working Group)
  • Erich Marschner, Verification Engineer, Mentor Graphics

Following are some notable excerpts from the discussion.

What's new in IEEE 1801-2013

Biggs: We took out some constructs that needed to be deprecated. We made some new additions. Syntax and semantics are a lot clearer and crisper now. We also have a new section on the attribution of pins and cells.

Marschner: This sounds like a laundry list of a lot of different things, and it is, but what may seem to be small changes improve a number of things. First, users have more fine-grained control over what their power strategy is. The second thing is the fidelity of the models. You can make sure what you specify actually represents the hardware.

Wang: More and more small companies are doing low-power design. What's most important is getting the methodology right. One thing we added in the 2013 version is an appendix that talks about methodology. This should be a very good start for people who have not been using a low-power flow.

What's driving adoption of power intent formats

Marschner: Over the last 30 years, HDLs [hardware description languages] have replaced schematics. The same thing is happening with power intent - there's a migration from ad-hoc methods towards standardized techniques.

Honnavara-Prasad: There's been an explosion in the number of power states. It's often in the 30s if not 100s. And more and more of them are software controlled, so it's not a HDL problem. It's a big challenge for verification.

Wang: To Sushma's point, verification will become a huge issue, and not just for functional verification but also for electrical verification.

Convergence between Unified Power Format (UPF) and the Common Power Format (CPF)

Biggs: Two years ago it was said that UPF and CPF are the same in every intent and different in every detail. But Si2 [Silicon Integration Initiative] has contributed the entire text of CPF to the IEEE, and Qi Wang of Cadence has been a significant contributor to the [IEEE 1801-2013] standard. I would not say we have format convergence, but there is a degree of methodology convergence.

Wang: The new standard does improve interoperability with CPF. What will make it most useful is if all the vendors support the new features.

Moving power intent beyond RTL

Marschner: Verification really ought to start in the front [of the design cycle]. If you wait, it will be a lot slower. You want to make sure you're making the right decisions for power management as early as possible in the flow. Today RTL, tomorrow we'll move up to the systems level.

Lee: We need to sit down in the next working group, for [UPF] 3.0, and see how we can move the standard so everyone can get that early power estimation.

What's next for IEEE 1801

Marschner: We are moving up the design chain to system-level power. We are moving forward with the next round of development in low-power model estimation. Anyone interested in participating in that process is welcome as a member of the committee.

Wang: We are talking with Si2 about their modeling approach. We can work together.

What you can do

Marschner: We need input from users, and if you would like to participate in the working group that would be great.

Honnavara-Prasad: I would encourage you to read the standard.

Note: If you want to follow this advice, IEEE 1801-2013 is available  for free download through the IEEE 1801-2013 Get Program.

Richard Goering

Related Blog Posts

Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

A CPF User Perspective on IEEE 1801 (UPF) "Methodology Convergence"

 

 

 

 

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