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Gary Smith at DAC 2013 – the $170M SoC Design is a “Myth”

Comments(0)Filed under: DAC, ESL, RTL, ITRS, virtual platforms, acceleration, emulation, embedded software, Gary Smith, models, architects, Design Automation Conference, virtual prototypes, software development, power models, DAC 2013, SoC design costs, IC design costs, $170M SoC, silicon virtual prototype

Analyst Gary Smith of Gary Smith EDA is not afraid to tackle what he sees as myths and misconceptions. At his annual night-before-DAC talk at the Design Automation Conference Sunday, June 2, he debunked a "myth" that SoC design will become too expensive for all but a handful of large companies.

Smith also predicted an $8 billion EDA market (excluding services) by 2017, said the electronic system level (ESL) flow is nearly complete, and claimed that the EDA industry is well positioned to take over the embedded software business. But he acknowledged that the transition from RTL design to ESL is going more slowly than he had expected.

Smith said there are lots of rumors that SoCs are so expensive that the semiconductor industry as we know it won't survive. Nonsense, he said. "Look at the numbers for a change. Don't believe the rumors."

Things are Improving

The basic problem with the doom-and-gloom predictions, Smith said, is that those who spread them don't think things will improve. So what will chip design be like in 10 or 20 years? Today, performance is really viewed as latency plus power. Power budgets (such as 5 watts) are design constraints. Fortunately, according to the International Technology Roadmap for Semiconductors (ITRS), dramatic improvements in low-power design technology are in store between now and 2027.

Smith talked about maximum usable gates due to power constraints. In 2011 we could use 11% of the total available gate count (of around 200M); in 2027 we'll be able to use up to 93% of the available gates (of around12.7B). To explain why, Smith presented an ITRS chart that showed a number of improvements in design technology that are expected between now and 2027.These include the silicon virtual prototype, intelligent testbench, reusable platform blocks, heterogeneous parallel processing, and transactional memory.

Now suppose the cost of the design is $50M, adding another constraint. In 2027 a design team will be able to design up to 5 billion gates - not 12 billion, but "not bad." What about a startup with $25M in venture funding? They can come within both their power budget and their cost budget and design up to 3 billion gates in 2027, Smith said - and you can do a lot with 3 billion gates. The bottom line - semiconductor startups will still be able to compete.

"Predictions that design will cost $170 million are just wrong," Smith said. "Intel, maybe, but that's for a custom design. We are not in a design crunch. Designs are opening up."

Progress in the ESL Flow

Smith then talked about the ESL flow and how it's evolving. With the advent of the silicon virtual prototype, and the increasing use of transaction-based acceleration and emulation, it's all coming together, he said. Gary Smith EDA has come up with some seat counts. For example:

  • Silicon virtual prototype - 129,346
  • Software virtual prototype - 326,747
  • Architect's workbench - 17, 435

The "disconnect" in this flow is that architects don't have enough information to do proper power-aware hardware/software partitioning. This task gets handed off to the RTL engineers, and they're not familiar with software development. Smith said, in fact, that the transition to ESL "is not working out as I expected. Not many RTL guys are moving up to ESL because they're not capable of grasping the software side of it."

Smith said it will take another 10-15 years for RTL to "fade" into ESL. Fortunately, a new generation of younger engineers has a better understanding of software. He cited Cadence architect and blogger Jason Andrews as a "prototype of the new ESL software guy."

Smith said there's an opportunity for EDA to extend its influence into the embedded software development world. We have (or should have) the models that the architects and software developers need. "You can give away your tools, but don't give away your models," Smith implored the EDA community. "This is where we monetize the embedded software world."

"We'll replace the whole embedded world, which is suffering from poor financial performance due to the free Linux software kernels that are out there," Smith predicted.

Smith concluded with his Q2 2013 forecast of EDA growth. The prediction is one of steady growth. Here are his predictions (again, not including services) for the next few years:

  • 2013 -- $6.1B
  • 2014 -- $6.5B
  • 2015 -- $6.7B
  • 2016 -- $7.5B
  • 2017 -- $8.3B

And there's plenty of room for EDA startups, Smith said. "This industry runs on startups."

There's a lot of good news for a lot of DAC 2013 attendees in Smith's talk this year.

Richard Goering

 

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