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Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

Comments(0)Filed under: Industry Insights, DFM, DRC, static timing, STA, multi-threading, multi-core, Cadence, extraction, signoff, physical verification, in-design signoff, optimization, MMMC, timing signoff, distributed processing, timing analysis, Tempus, timing closure, parallel processing, path-based, multithreading, Devgan, graph-based, FineSim, Magma, signoff division, multi-corner, Anirudh Devgan, Silicon Signoff and Verification

Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution. Tempus provides up to an order of magnitude faster performance than existing solutions, scales to handle full-flat analyses of designs with hundreds of millions of instances, and comes with an integrated optimization environment for signoff closure.

The Cadence vision of Silicon Signoff and Verification, however, goes well beyond static timing analysis. In this interview Devgan talks about the Cadence Silicon Signoff and Verification mission, his background, key signoff challenges, in-design signoff, static timing analysis at advanced nodes, and key features of Tempus.

Q: Anirudh, what is the Cadence mission in the Silicon Signoff and Verification area?

A: We see a big hole in the signoff space. The problems are getting more difficult to solve, and the solutions are not keeping up with those problems. There is a huge opportunity for Cadence to provide better solutions. Our mission is to provide best-of-breed, world-class tools into the market.

Q: What products are part of Silicon Signoff and Verification?

A: We include all aspects of signoff and physical verification. That includes timing, power signoff and integrity, transistor-level and gate-level extraction, DRC and all aspects of physical verification, and also design for manufacturability.

Q: What does your role include?

A: I'm responsible for Silicon Signoff and Verification in terms of the resources for developing R&D, product marketing, product engineering, and business development.

Q: What were you doing before taking this position?

A: I joined Cadence in May 2012. Before that I was general manager and corporate vice president of Magma's Custom Design business unit. We launched several successful products including FineSim, which became the leading circuit simulation product. We launched Titan for analog design and SiliconSmart for characterization.

I was at Magma for seven years. Before that I was at IBM for 12 years in different roles, starting with research, and then in different product groups. I have a PhD in EDA from Carnegie Mellon. I would basically say that my background is in implementation, signoff and simulation.

Q: What do you see as the key signoff challenges that customers are facing today?

A: I think there are three key signoff challenges. The first challenge is performance and capacity. It is taking much longer to sign off chips. That's because the chips are getting bigger, the number of modes and corners and scenarios that have to be analyzed is getting larger, and the capacity of the tools to handle the chips is not there.

The second problem is accuracy. At lower geometry nodes, analysis becomes more analog in nature. It needs to be a lot more accurate. The accuracy problem translates into pessimism or margins in analysis. That typically leads to chips with bigger area, or requires more time to do design.

The third big problem is that analysis is only one part of the problem - closure, which includes optimization, takes a long time. Even if customers can analyze, they often don't know how to fix problems. Manually fixing them, or using a combination of tools, takes a very long time. Analysis may take a week, but closure and optimization could take six weeks.

Q: How can Cadence help customers solve these challenges?

A: We will have tools and technologies that fundamentally address these challenges. We will provide new algorithmic solutions. You will see us announce new products that address these challenges, and we will start off with static timing analysis, which is a critical area in signoff.

Q: What is "in-design signoff" and why is it important?

A: In-design signoff basically means the ability to combine design, implementation and signoff together in the design process. For example, timing analysis and place and route can share the same timer. This allows you to not only do signoff at the end of the process, but to do signoff-level analysis during the process.

One advantage of in-design signoff is that the signoff process can be done earlier and done much faster. You can do signoff during implementation and get early visibility into how the chip is going to operate. The second value is to include implementation in signoff, and therefore do optimization or fixing during the final signoff analysis.

Q: Looking more specifically at static timing analysis, what requirements and challenges arise at advanced processing nodes?

A: At 90nm or 65nm, only a few scenarios of modes and corners need to be analyzed. At 20nm or 16nm, hundreds of modes and corners need to be analyzed. The next thing that has gone up is the size of the circuits. 100 million instances is a not uncommon design size, and the designs have expanded significantly.

Because of lower voltages, there are more analog effects. The timing accuracy needs to be much higher than it was at lower nodes. One way to add accuracy and reduce pessimism in timing is through path-based analysis. Traditionally when you run timing it is graph-based. The reason people don't do path-based analysis is because it is slow. It needs to be efficient.

Q: What new capabilities is Tempus bringing to timing signoff?

A: We are very excited about our new timer. This is a new implementation originally developed at Cadence, and one of the key features is the ability to run timing on a large number of CPUs and machines in a parallel mode. In EDA, a lot of parallelism had been localized to multi-threading, which only gives four or eight CPUs. But with the new Tempus architecture we can run it on 50 or 100 CPUs and give a dramatic performance improvement, and also dramatic capacity improvements.

Secondly, we have a new approach to path-based analysis. We believe the industry needs to go to path-based analysis and we have a new algorithm that is very efficient and also utilizes multi-threading.

Third, because we have integrated our timer and place and route inside Cadence, we have an optimization environment that is run within signoff timing. This can close the last mile, the last optimization problems in your design process. So something that might previously take two weeks can be done in a day, or half a day, in this integrated closure environment.

Q: What are customers telling you about Tempus?

A: We are getting an extraordinary response from the customers. They are excited about the ability to run very large chips in a short amount of time, and the ability to improve accuracy with path-based analysis. A task that used to take them 20 or 25 hours can now be done in one to two hours. A task that would take a lot of iterations between place and route and signoff can be done in only one or two iterations.

So, our initial customer engagements have been very positive and we look forward to taking [Tempus] to a wider customer base.

Q: Beyond static timing analysis, what else can we expect in the Silicon Signoff and Verification area?

A: We want to have best of breed products in each and every category. As we go through the other aspects of signoff we are working on fundamental improvements we will talk about in the coming months.

Richard Goering

Note: In a short video interview, Anirudh Devgan discusses signoff challenges and the Tempus Timing Signoff Solution. You can view it here.



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