Home > Community > Blogs > Industry Insights > dac 2013 panel to reveal finfet deployment challenges
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DAC 2013: Panel to Reveal FinFET Deployment Challenges

Comments(0)Filed under: ARM, DAC, FinFets, Texas Instruments, TI, TSMC, Cadence, Design Automation Conference, 16nm, DAC 2013, FinFET deployment, FinFET panel, FinFET lunch, Brian Fuller

FinFET transistors represent one of the most exciting new technology developments in recent years, and no wonder - these 3D devices promise huge power and performance advantages at 16nm and below. But the deployment of advanced node designs with FinFETs raises a number of challenges. At the Design Automation Conference (DAC 2013) Tuesday June 4, a panel of experts will discuss these challenges and consider the solutions that are needed.

The discussion will be part of a Cadence-sponsored lunch panel open to all DAC attendees. The lunch and panel will be held 11:30 am - 1:30 pm at the Austin Convention Center in Ballrooms E and F (see Convention Center map here). Panelists will debate issues including process development, tool support, ecosystem dynamics, design challenges, and power/performance tradeoffs. Panelists will represent a spectrum of viewpoints including foundry, IP, EDA, and SoC design.

The panel will be moderated by my former EE Times colleague Brian Fuller, who recently joined Cadence as content director/editor-in-chief. Panelists include:

  • Vinod Kariat, Cadence
  • Suk Lee, TSMC
  • John Heinlein, ARM
  • Anthony Hill, Texas Instruments

This informal panel will essentially be a guided conversation about the challenges of getting FinFETs into production. It will be interactive, so bring your toughest questions. But first you need to register. To do so, click here. For a complete listing of Cadence activities at DAC, see our DAC microsite.

Richard Goering

Related Blog Post

Cadence DAC 2013 and Denali Party Update

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.