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DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions

Comments(0)Filed under: Industry Insights, DAC, SoC, verification, AMS, analog/mixed-signal, Cadence, Tensilica, custom/analog, System Development Suite, Design Automation Conference, EDA360 Theater, semiconductor IP, user presentations, Cosmic Circuits, DAC 2013, Cadence Theater, Forte, customer, partner, SoC IP

If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference (DAC 2013) in Austin, Texas June 3-5. At last count nearly 50 customer and partner presentations were scheduled between 9:30 am Monday, June 3, and 5:30 pm Wednesday, June 5. These presentations are open to all DAC attendees and no reservations are required.

Similar presentations were offered in 2012 and were very successful. They typically attracted standing-room-only crowds and provided an informal, interactive setting with good audience participation. Audio recordings are still available for many of the 2012 talks. This year's roster includes half-hour presentations from customers, IP providers, foundries, consultants, and Tensilica (recently acquired by Cadence). As noted below, there's also a joint presentation by Cadence and Forte Design Systems.

Cadence Theater at DAC 2012

A complete, updated listing of the Cadence Theater presentations is located here. Rather than duplicate the entire list, I've identified several key categories and listed some of the relevant presentations.

Functional Verification

Monday 10:30 am - Texas Instruments, Experience Migrating to the UVM
Monday 11:00 am - Freescale, Best Practices in Verification Planning
Monday 12:00 pm - Contemporary Verification Consultants, e-asing your Verification Pains with IEEE 1647 and IES
Tuesday 11:00 am - Texas Instruments, Highly Scalable Multicore ARM A15 Verification with Specman/e
Tuesday 5:00 pm - Siemens, Musings on Advanced Functional Verification with Specman/e in FPGAs for Medical Devices
Wednesday 9:00 am - Marvell, Low Power Verification using Conformal Low Power
Wednesday 9:30 am - Verilab, UVM Multi-Language with e, SystemVerilog, SystemC, C/C++

System Development Suite/HW-SW Co-verification

Monday 9:30 am - Freescale, Implementation of a Multi-Threaded 64-bit Power Architecture Core on the RPP FPGA-based Prototyping System
Monday 12:30 pm - AMD, Palladium XP
Monday 2:00 pm - ARM, ARM DS-5 Enabling Debug for the System Development Suite Engines
Monday 2:30 pm - Broadcom, Faster System Bring-up with an Embedded Testbench on Palladium
Tuesday 3:00 pm - Freescale, Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis
Wednesday 11:30 am - Bluespec, The Best of Both Worlds - Combining Virtual and FPGA-Based Prototypes
Wednesday 2:30 pm - Freescale, Palladium XP
Wednesday 3:30 pm - Dini Group, Hardware Solutions for FPGA-Based Prototyping

Custom/Analog and Mixed Signal

Tuesday 10:30 am - Silicon Labs, Digital-Centric Mixed-Signal Solution
Tuesday 5:30 pm - IBM, Multi-Pattern Design Within Virtuoso 12.1
Wednesday 1:30 pm - ARM, Cortex-M0 and Cortex-M0+; Tiny, Easy, and Energy Efficient Processors for Mixed-Signal Applications
Wednesday 5:30 pm - NXP, Layout-Dependent Effects; Exploring LDE Analyzer 

SoC/Semiconductor IP

Monday 11:30 am - ARM, AMBA Interconnect IP
Monday 5:30 pm - ARM, ARM Cortex-A15 Hard Macro and Artisan POP Proof Points
Tuesday 2:30 pm - Tensilica, Customizable Processor Basics
Tuesday 3:30 pm - ARM, ARM Cortex-A15 and A7 (big.LITTLE Processing for ARMv7 Architecture)
Wednesday 11:00 am - Tensilica, Imaging DSP
Wednesday 12:00 pm - Oracle and Cosmic Circuits, SoC IP
Wednesday 3:00 pm - Tektronix, SoC IP

A Sampling of Other Presentations

Monday 1:00 pm - Cisco, Managing PCB Constraints
Tuesday 10:00 am - IBM, Die Sizing with Cadence Chip Planning System
Tuesday 11:30 am - Cadence and Forte, How to Broadly Deploy SystemC High-Level Synthesis for Production Hardware Design
Tuesday 12:00 pm - Micron, HMC (Hybrid Memory Cube): The New Standard in Memory Performance
Tuesday 12:30 pm - Marvell, SoC Interconnect Analysis for Effective Verification, Architectural Exploration, and Post-Silicon Debug

All presentations are at the Cadence booth, #2214. You can view the latest schedule here. See you at the Theater!

Richard Goering

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