If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation March 12, 2013, given by Jack Benzel (right), expert engineer at Avago Technologies.
Avago, which originally was part of Hewlett-Packard, provides an extensive range of analog, mixed-signal, and optoelectronic components and subsystems. Benzel's group works on very large, high performance networking ASICs. Earlier this year, Cadence reported that Avago had increased performance of a 28nm networking chip by 57% using GigaOpt technology in the EDI System (see press release here).
GigaOpt first came to light with the EDI System 11.1 release (see blog post here), and its intent is to provide a common optimization engine across the IC physical design flow. Benzel's CDNLive presentation focused on new preRoute capabilities that are going "mainstream" in EDI 13.1, where GigaOpt is the default optimization technology throughout the implementation flow (both pre-route and post-route).
In the standing-room-only CDNLive presentation, Benzel first cited some challenges he encountered while using older versions of EDI System. He then provided detailed information about the difference he experienced with GigaOpt preRoute. Specifically, he talked about route-driven optimization, advanced re-buffering, path balancing, path compaction, and a focus on total negative slack (TNS) optimization. In the case of TNS, he pointed to orders-of-magnitude improvements compared to earlier software.
A few years ago Benzel was having problems with buffering. Sometimes there was too much, sometimes too little - and some hand placement of muxes and registers was required. Another problem was an initial over-subscription, and then under-subscription, of the upper metal layers where routes can run much faster than on lower layers at advanced nodes. Benzel brought these challenges to the attention of Cadence at a meeting in early 2012.
Benzel then started to do some analysis on his own, and found there was much to be gained by advanced layer selection and good buffering. Using some seed code provided by Cadence, he developed a Tcl script that improved the buffering and reduced TNS by fixing just a few paths. But he didn't have to continue this effort, because Cadence provided transforms with the GigaOpt preRoute technology to address his requirements.
The new GigaOpt preRoute features broke through issues Benzel had been dealing with for several years, while at the same time improving post-route correlation and reducing run times, he explained. The new capabilities replaced engineering-intensive, arduous manipulation of the block build process.
Benzel noted that GigaOpt preRoute uses the same Advanced Analysis Engine (AAE) that EDI System employs post-route. GigaOpt, he said, is "a proven technology, it's multi-threaded, scales well, and is easily extensible with new transforms. And it's the default in 13.1."
Transforms Boost Quality of Results
The most powerful transform, Benzel said, is route-driven optimization, which lets designers make full use of the low RC (resistance-capacitance) upper layers of metal where interconnect can run 6-10X faster with good buffering. The optimization promotes long-haul, timing-critical nets to the upper metal layers. It uses a route resource manager to avoid over-subscription on the upper layers, which would lead to congestion. Using an analogy to Denver traffic, Benzel said "it's really about taking the interstate, but that's a limited resource."
Benzel showed a comparison in which lower metal layers provide a delay of 710ps/mm, whereas the thicker upper layers provide just 120ps/mm. "This is really important for high-performance, low-latency designs," he said. He also showed a before-and-after GigaOpt comparison of worst-case paths, noting the substantial slack time improvement with GigaOpt.
The next transform Benzel discussed was advanced re-buffering. Here, the optimizer dynamically alters buffering as the route topology changes. This is actually a "grab bag" of various transforms, he said. "Sometimes it will rip out a large buffer tree and re-buffer it if things aren't working right. It's been able to do that because of the higher performance engine."
Another transform is path balancing, which can move registers in order to balance negative slack on one side with positive slack on another. Yet another transform is path compaction, which finds failing timing paths and reduces the "bounding box" that surrounds the path. This reduces the topology of a path, and cleans up non-optimal buffering.
Finally, GigaOpt optimizes high-fanout paths to remove large TNS contributors. "The classic engine before GigaOpt really ran on worst negative slack. The new GigaOpt strategy goes after TNS contributors in your design," Benzel said. He pointed to an example in which one path is driving 400ns of TNS. "I can fix that guy with maybe a few buffers and wipe out 400ns," he said.
All Together Now
With "all cylinders firing," Benzel said, the transforms he discussed all "work symbiotically together." He showed one comparison in which GigaOpt preRoute provided the following outcomes:
- Run time reduced from 6.5 hours to 4 hours for placed design
- Less than half the memory footprint required earlier
- Over an order of magnitude TNS reduction
- Reduced density due to smarter buffering
- A placed design takes a little more time - but optimization run-times are nearly cut in half
He showed another comparison in which five challenging blocks were given to Cadence for evaluation. For one block, TNS was 3,400ns pre-GigaOpt, and 0.37ns with GigaOpt. Benzel also noted that GigaOpt preRoute results are deterministic. With two 5-CPU block builds, one with numerous older mode settings and another with minimal mode settings, the output Verilog was identical.
And GigaOpt will keep getting better, he said. "Because of the nature of this technology they can just bolt in transforms. They can go out, find an issue, and write a transform for it."
Benzel's CDNLive presentation slides are available in the CDNLive Silicon Valley 2013 proceedings archive. A Cadence log-in is required. For more information about EDI System 13.1, click here. For more information about Avago, see the company web site.