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Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

Comments(0)Filed under: Industry Insights, Encounter, EDI, Micron, Power, Electronic Design Processes, 3D, TSV, Gary Smith, 3DIC, yield, 3D IC, 3D-IC, IC/package co-design, Cadence, Mentor, thermal, extraction, design rules, foundry, 2.5D, EDPS, silicon interposer, stress, OSAT, hybrid memory cube, HMC, 3D die stacks, redundancy, TSV modeling, 3D stacking, Herb Reiter, HMCC, Brandon Wang

3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good reflection of the tone of the panel, where industry experts considered challlenges and solutions in 2.5D silicon interposer and 3D stacked die packaging.

Now in its 20th year, EDPS is a small but influential IEEE workshop that brings together some of the world's top experts in electronic design methodologies. (I previously blogged about an electronic system level (ESL) session at this year's EDPS.) The 3D-IC session included three presentations and a panel discussion. Panelists were as follows, shown left to right in the photo below:

  • Mike Black, technology strategist, Micron
  • Dusan Petranovic, interconnect modeling technologist, Mentor Graphics
  • Herb Reiter, EDA consultant
  • Brandon Wang, marketing director for 3D-IC solutions, Cadence
  • Gary Smith, analyst, Gary Smith EDA

Gene Jakubowski, CEO of interconnect analysis provider E-System Design, served as panel moderator. Petranovic, Wang, and Black gave pre-panel presentations that I'll briefly summarize below. Their slides are available from the EDPS 2013 program listing.

Tool Support and Silicon for 3D-ICs

Petranovic (Mentor Graphics) discussed verification and extraction challenges for 3D stacks. He described issues in through-silicon via (TSV) modeling including depletion region effects, interactions between TSVs, interaction between TSVs and interconnects, and impact of TSVs on device performance. He discussed the advantages and challenges of single TSV models, compact parameterized models, and field solvers, and presented a field solver-based 3D-IC extraction solution.

Wang (Cadence) presented a "holistic" approach for 2.5D and 3D realization. He first discussed technologies that are on a short-term, medium-term, and long-term path to 3D-IC, noting that EDA work must start at least 3-4 years earlier. "This year silicon interposer will take off," he said. "3D stacking will still be limited to the memory interface, but in the future it will not be limited to memory."

What does 3D-IC change in the EDA world? Wang identified a number of requirements, including package/silicon co-design, new layout layers, new extraction features, inter-process DRC/LVS, cross-die power and signal integrity, cross-die timing closure, and thermal analysis. He showed how Cadence meets these requirements with an integrated 3D-IC solution that includes flexible and connected implementation "cockpits" (including Virtuoso custom design, Encounter digital design, and Allegro IC packaging).  He also noted that the Cadence solution provides a wide range of analysis tools, including some of the power integrity and thermal analysis software that Cadence acquired last year from Sigrity.

Black (Micron) presented the Hybrid Memory Cube (HMC), an innovative 3D stack that places DRAMs on top of logic. It claims to offer up to 15X the bandwidth of a DDR3 module, 70% less energy usage per bit than existing technologies, and a 90% space reduction compared to today's RDIMMs. Black said the first HMC device will start shipping later this year. But Micron is not going down this path alone. Black talked about the Hybrid Memory Cube Consortium, which is promoting adoption and acceptance of an industry standard serial interface for the HMC. (Cadence is both a member and a Micron ecosystem partner).

Here are some interesting points made during the panel discussion.

Yield and Redundancy

Reiter - What I would like to see happening inside 3D-IC cubes is redundancy. Memories already have it, but we should also consider redundancy at the logic level. It's cheaper to add 5% to the die size than to take a 10% or 20% yield hit.

Wang - There are some ways that 2.5D interposers use redundancy. The TSV routing is double track, just in case one fails. The Cadence EDI [Encounter Digital Implementation] System allows the option of routing multiple RDL [redistribution] layers into a microbump. Also, you can use combination bumps. If you have 4 bumps and one fails, the other three can carry on normal operations.

Stress and Design Rules

Wang - Currently foundries are doing very accurate calculation of TSVs, including TSV stress impact to the logic nearby. But I do believe, as they get ready for mass production, they will come out with a set of rules. There will be a keep-out barrier for TSVs.

Petranovic - I agree that as much as possible, foundries will go with rules. But TSVs are not the only source of stress. The bumps and connections between the dies can be worse.

Foundry, OSAT - Who Does What?

Reiter - Let me address the question of the power shift between foundry and OSAT [outsourced assembly and test] provider. The foundry business today has a 65-70% margin. Assembly houses have a 20% margin. So there is an R&D budget problem now on the assembly side. We need to give OSATs more value in the food chain and more opportunity to invest in this [3D-IC] technology.

Vision or Reality?

Audience question - What happened to the vision of 3D-ICs that people had four years ago, and will it ever come back?

Reiter - In the last four years we went from a set of marketing slides to a set of engineering slides. 16 or 20 layer stacks will be very expensive and difficult to design. But I do expect that, in the next 2-3 years, we will see 40 to 50 die stacks in the computing world.

Getting Hotter

Wang - Everybody knows that thermal issues are challenging right now. Silicon die happens to be the best conductor. A 2.5D silicon interposer doesn't stack dies. That technology is truly ready to take off this year and next year. For 3D stacks for mobile applications, portable heat-dissipation package technology is still in research. It's probably two to three years away.

If it's not heterogeneous, like a memory stack, it's not such a big deal - each die is working at roughly the same temperature.

Black - A lot of work is being done to try to advance the cooling. We don't see [DRAM] sitting on top of anything that's going to run more than about 15 Watts.

Power Management for 3D-ICs

Reiter - The beauty of putting a logic layer under a memory stack is that you can add a lot of intelligence. You can apply the same power management features used in an SoC to a 3D stack. It may be easier to have power domains at the die level. And you can mix analog and digital and do a lot of stuff in analog that is lower power than the digital.

Conclusion - 3D-IC is "Better Than Expected"

Audience question - Gary, what is your perception of 3D-IC? When do you see it moving forward in a big way?

Gary Smith - For the last 5 years I've been saying 2015, but I'm a little more optimistic now and I think maybe it's going to be 2014. It's going better than we expected. You're not hearing the grandiose plans you used to hear - it's really down to practical issues. High-performance computing is an obvious target and the main driver is going to be power. Most of it will be memory on top.

TSVs are hard. It's been a real tough go but it looks like we've got a handle on it.

Richard Goering

 

 

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