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TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies

Comments(0)Filed under: EDA, Industry Insights, lithography, EUV, Double Patterning, E-Beam, DRAM, 28nm, 3DIC, TSMC, 20nm, 3D-IC, Cadence, design rules, wide i/o, 2.5D, FinFET, 10nm, CoWoS, TSMC Forum, 16nm, Cliff Hou, TSMC 2013, TSMC Symposium, 3D stacked die, Jack Sun, Global 450, wafer level package, J.K. Wang, JK Wang, 450mm wafer, electron beam, WLP, 20SoC

The TSMC 2013 Technology Symposium, held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies, as well as promising development work with 10nm FinFET and true 3D-IC stacking.

Keynote speakers included Morris Chang, TSMC founder and CEO, who provided a semiconductor industry overview and company update (see blog post here). Subsequent keynote speeches were given by TSMC executives Jack Sun, Vice President of R&D and Chief  Technology Officer; Cliff Hou, Vice President of R&D; and J.K. Wang, Vice President of Operations, 300mm Fabs.

Sun (left) began his talk with a look at the human brain, a 3D structure that has the equivalent of about a trillion transistors and only consumes 20 watts. State-of-the-art systems on chip are nowhere near that performance and power efficiency, so how can we get closer? "Going into the future we don't have to resort to monolithic integration alone," he said. Instead, we can combine chip scaling with copper through-silicon via (TSV) technology and close the interconnect gap between chips.

20nm, 16nm and 10nm Progress

While TSMC has four "flavors" of its 28nm process, there is one 20nm process, 20SoC. "20nm planar HKMG [high-k metal gate] technology has already passed risk production with a very high yield and we are preparing for a very steep ramp in two GIGAFABsTM," Sun said.

Sun noted that 20SoC uses "second generation," gate-last HMKG technology and uses 64nm interconnect. Compared to the 28HPM process, it can offer a 20% speed improvement and  30% power reduction, in addition to a 1.9X density increase. Nearly 1,000 TSMC engineers are preparing for a "steep ramp" of this technology.

For the upcoming 16nm FinFET technology, Sun said, "our SRAM yield is fantastic and we are ahead of our plan. We are pulling in the risk production schedule for the end of this year." He said the process node uses "industry leading FinFET technology" that provides superior gate control, reduced channel doping, low threshold variability, good low voltage capability, and power efficiency.

The next technology node is 10nm FinFET, which TSMC expects to release by the end of 2015. Sun said it will provide a "full node advancement" in power, performance and density compared to 16nm. What does that mean? Historically, Sun said, a new process node offers close to 2X density improvement, and can boost performance about 25%-30% at the same power. But with FinFETs, he said, TSMC can exceed that trend line and possibly provide 35% to 40% power savings at the same speed.

Advanced Patterning

One issue that cuts across all these process nodes is the need for double or multiple patterning. At 10nm, in particular, "we have to employ novel patterning techniques," Sun said. TSMC has made improvements to immersion lithography and has also developed an extreme ultra-violet (EUV) process for the 10nm node. TSMC has in-house EUV tools and has made progress in overcoming two EUV challenges - source power requirements, and throughput.

TSMC is also investigating multiple e-beam technology, which, as Sun said, "has fine resolution but is just too slow." But parallelism can help improve throughput. For production use, throughput needs to be more than 100 wafers per hour. If this can happen, e-beam "does show promise in the future," he said.

For immersion lithography, TSMC has come up with "design friendly" rules for 20nm and 16nm. "We'll take care of the two-color decomposition and mask-making process," Sun said.

Going 3D

TSMC introduced its CoWoSTM process in 2012. Using a technology often called "2.5D" integration, CoWoS places chips on a silicon interposer substrate. Sun said TSMC has been doing a lot of work to enable this technology, including test vehicles and work with partners, and that in-house production yield has been very high.  TSMC has demonstrated a CoWoS package with SoC, embedded DRAM, and third-party Wide I/O DRAM integrated together.

Sun noted that a technology called advanced fan-out wafer level package (WLP) is a "cousin" of the silicon interposer, with less density and lower cost. TSMC has qualified WLP for production. Meawhile, Sun said, TSMC is moving ahead with 3D die stacking and has already demonstrated vertical chip stacking in 28nm technology.

Design Enablement

All this new technology sounds promising, but how will it be implemented? Cliff Hou (right) tackled that subject with his keynote on "design enablement and the ecosystem." He made the following points about the 20nm and 16nm nodes:

  • 20nm is production-ready now, with numerous EDA tools qualified and 185 design kits available. All foundation IP and some critical interface IP has passed qualification.
  • FinFET technology requires some new tool capabilities, including 3D parasitic extraction, a new parameter (NFIN, the number of fins) for the custom IC flow, FinFET-aware circuit simulation, and ESD (electrostatic discharge) analysis.
  • For the 16nm FinFET node, "most of the EDA tool ecosystem will be ready for you to start design by the end of July."
  • The 16nm node uses 7.5 track libraries. This provides better performance than the 9-track libraries used at the 20nm node.
  • Comparison of 16nm FinFET 7.5T to 20nm 9T: 37% less power at the same speed, or 26% better performance at the same leakage.

Hou noted that TSMC worked with partners SK Hynix and Cadence to tape out a CoWoS test chip. Hynix provided the DRAM and Cadence provided the Wide I/O PHY and controller. This shows, Hou said, that TSMC can integrate commodity DRAM into its CoWoS technology with a very good yield. Further, he noted, "we are working on a true 3D stacking project right now" involving an SoC and stacked DRAM.

Manufacturing and Capacity

JK Wang (left) provided an update about TSMC's formidable manufacturing capability. He noted that the company currently has one 6" fab, six 8" fabs, and three 12" fabs. TSMC is continuing its capacity expansion at the 12" fabs. Mass production for 20nm is planned for the first half of next year.

In particular, Wang talked about Fab 15, which started from scratch in June 2010. It ramped from zero to 50K wafers/month, and TSMC expects to reach 100K wafers/month in 5 months.

Wang also affirmed TSMC's commitment to 450mm wafer production. He spoke of TSMC's role in the Global 450 Consortium at the Albany NanoTech Complex in Albany, N.Y. With TSMC in a leadership role, the consortium will demonstrate and deploy 450mm wafer tools and process capabilities. "TSMC will lead the industry towards an effective 450mm wafer size transition," Wang said.

(Note: On April 8, 2013, Cadence announced an agreement with TSMC to strengthen the design infrastructure for 16nm FinFET technology. You can read the press release here.)

Richard Goering

Photos from Taiwan Semiconductor Manufacturing Co. Ltd.

 

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