Home > Community > Blogs > Industry Insights > videos presentations highlight front end ic design methodologies
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Videos, Presentations Highlight Front-End IC Design Methodologies

Comments(0)Filed under: ARM, Encounter, RTL Compiler, DFT, Logic Design, synthesis, ECOs, Conformal ECO, equivalence checking, Encounter Test, logic synthesis, RTL synthesis, RC, front end design, physical aware synthesis, FED Technology Summit, front end design summit, front-end, FED, test coverage

Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are now available at the FED Technology Summit archive site (Cadence.com log-in required to view proceedings).

The following presentations and videos are available:

  • Front-End Design Summit - R&D Welcome, Andy Lin, Cadence (video, presentation)
  • Physical Aware Synthesis Challenges on Flash Memory Designs - Dinraj Shetty, Spansion (video, presentation)
  • Physical Aware Synthesis for High Performance Designs: Past, Present and Future - Jean-Charles Giomi, Cadence (video, presentation)
  • RC/LEC Lessons Learned on a High Performance Custom Protocol Processor - Paul Everhardt, Chelsio (video, presentation)
  • A Systematic Test Implementation Methodology - Jon Haldorson, PMC-Sierra (video, presentation)
  • Achieving Your Coverage Goals on Complex Designs Using Encounter Test - Mike Vachon, Cadence (video, presentation)
  • Shared Conformal ECO Experiences - Ajay Bhandari, Cisco (video, presentation)
  • How Can "WI" Help Make Your Verification Easier? - Kei-Yong Khoo, Cadence (presentation)
  • Enabling a More Efficient LP Flow when Using Legacy Libraries - Frank Hsu, VIA Telecom (video, presentation)
  • Leveraging ARM and Cadence Collaboration for Fastest TTM and Best PPA on ARM Cores - Paddy Mamtora, Cadence

To view any of these videos or presentations, click here. More information about Cadence front-end solutions is available here.

Richard Goering


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.