Think RTL synthesis is a solved problem that needs no further discussion? Think again. In a keynote speech at the recent International Symposium on the Quality of Electronic Design (ISQED 2013) Sanjiv Taneja, vice president of product engineering at the Cadence Front-End Design group, showed how advanced node IC design is raising new requirements for "physical aware" logic synthesis.
The keynote was titled "Physical Aware, High Capacity RTL Synthesis for Advanced Nanometer Designs." Taneja discussed the physical effects of interconnect and congestion, and showed how these effects place new demands on RTL synthesis starting with logic structuring, global mapping, and incremental optimization. He illustrated the capabilities that are needed in order to model physical effects in synthesis.
Why is a new RTL synthesis approach needed? The mobile revolution is driving a new generation of devices, Taneja said. 20nm ICs are often in the "multi GHz" range with interconnect delay and routing congestion limiting the performance, and they may have 100M+ placeable instances. Add to that complex clocking schemes, power management techniques, and lithography and design for manufacturability (DFM) concerns, and massive complexity is the outcome.
Interconnect and Congestion Challenges
Taneja discussed two advanced node challenges for RTL synthesis - physical interconnect modeling and routing congestion. Early stages of RTL synthesis such as logic structuring and global mapping can have a significant impact on the structure of a logic circuit, but limited physical design information is available. By the time the synthesis process has reached the late timing correction (incremental optimization) stage, the network structure can only be changed in a very limited way.
The logic structure has a significant impact on the routability and wiring congestion irrespective of the floorplan and placement algorithm. It is therefore important for placement and route topology to be modeled and abstracted with the right level of accuracy at the early stages of RTL synthesis to allow for physical-aware structuring and mapping.
Physical-aware synthesis (right) combines logical and physical synthesis, and will produce more optimized results than traditional approaches (left)
Routing congestion can result from two sources - a poor floorplan, or the netlist structure. If the problem is the floorplan you can usually move some blocks around and change pin positions to clear up the congestion. If it's the inherent structure of the logic netlist, the only option is to re-synthesize it while taking the routing congestion charartistics in consideration. "The idea here is to anticipate early on, in the RTL synthesis stage, the impact of the netlist structure on routing congestion," Taneja said.
Many years ago, synthesis providers developed "wire load" models to estimate interconnect delays. These models were very simplistic and had run out of steam even before 40nm. Several years ago, Taneja noted, Cadence introduced the notion of "physical layout estimation" to provide better modeling of interconnect. This is a physical modeling technique that uses actual design and physical library data to estimate wiring delays.
While physical layout estimation is effective in estimating the wire delays for short nets, it is inadequate for the long nets. The physical placement of circuit components, in contrast, allows an accurate identification of the long nets. Once these nets have been identified, the topology of these nets -- including detouring and via effects -- must be modeled and mapped to the layer stack, as opposed to just using an average RC value for each layer.
Layer assignment has a big impact on interconnect delay. At 20nm, Taneja said, there may be as much as two orders of magnitude difference in resistance per unit length from the bottom to the top of the metal layer stack. This difference requires "layer aware optimization" during synthesis.
Taneja also discussed some congestion optimization techniques. One is morphing, which incrementally re-distributes white space around placed instances to reduce pin access problems. Another approach is congestion-aware and placement-aware incremental optimization, which incrementally places new gates to reduce congestion through real-time congestion estimation.
Taneja stressed the need for congestion-driven design for test (DFT) logic placement. Test logic tends to be highly concentrated with a large number of I/Os in very small regions, further complicating the routability of a design, he noted. Additionally, the widespread use of ATPG has introduced very dense compression/decompression logic, which is a hot-spot for congestion.
Taneja listed some needed synthesis capabilities for advanced nodes. These include:
- Multi-Vt leakage optimization
- Improved skew degradation estimation
- Layer assignment estimation and modeling
- Advanced on-chip variation (OCV) support
Taneja provided some further details about physical aware structuring and physical aware mapping. One impressive data point is that physical aware mapping can boost timing by up to 20 percent.
A final point is the need for hierarchical flows to manage capacity for large designs. This requires prototyping and partitioning, assembly of the top-level design, and top-level timing closure. Accurate timing analysis is still needed, and can be provided by interface logic models (ILMs), which do not abstract timing but discard what is not needed for modeling block-level boundary timing.
"The key point is that you have to be congestion aware and physical aware right from the very first steps in logic synthesis, from structuring and mapping all the way to incremental optimization," Taneja concluded. It sounds like synthesis R&D experts aren't going to run out of work any time soon.