Home > Community > Blogs > Industry Insights > why cadence agreed to acquire tensilica and how it can ease soc design
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Why Cadence Agreed to Acquire Tensilica – And How It Can Change SoC Design

Comments(0)Filed under: Industry Insights, SoC, IP, embedded software, Cadence, Tensilica, design IP, Cosmic Circuits, IP subsystems', configurable IP, Cadence and Tensilica, DSP, dataplane, Xtensa, Eclipse, DPU, Cadence buys Tensilica, dataplane processing unit

On March 11, 2013, Cadence announced an agreement to acquire Tensilica, a successful provider and market leader in dataplane processing IP.  By providing a more complete solution for system-on-chip (SoC) design, the acquisition will facilitate a new generation of highly differentiated, low-power, high-performance SoCs that can be brought to market quickly.

To appreciate the significance of the pending acquisition, it's important to understand where and how Tensilica fits into the SoC design ecosystem. Tensilica pioneered the development of highly specialized, programmable dataplane IP that works synergistically with industry-standard embedded CPU architectures. These specialized IP cores, called Xtensa® Dataplane Processing Units (DPUs), support a wide range of embedded data and signal processing applications in the dataplane, allowing customers to quickly develop SoCs optimized for their applications.

Tensilica offers pre-customized, application-specific DPU subsystems for high-volume applications such as mobile wireless, network infrastructure, auto infotainment, and home applications. Designers can also use automated Tensilica® tools to create fully customized instruction sets for specialized functions such as signal processing, network processing, solid state storage, security and encryption, and more. The tools generate a matching software tool set, models, EDA scripts, and everything else needed to get into production quickly.

Key advantages of the Tensilica DPU architecture include the following:

  • Customized DPUs can be tuned for an application, achieving the optimal power, performance, and area efficiency
  • Configurable data and signal processing IP has both time-to-market and flexibility advantages over customized RTL hardware blocks
  • The Tensilica architecture allows programmability after tapeout, allowing extensibility and reducing the risk of silicon respins
  • Xtensa DPUs provide application-specific subsystems for the dataplane of the SoC. DPUs are complementary to industry-standard CPUs and GPUs

Tensilica may be a technology pioneer, but it is not a small startup. Founded in 1997, the company has more than 200 licensees, including system OEMs and 7 of the top 10 semiconductor companies, and its licensees have shipped over 2 billion cores.

A Growing IP Portfolio

Cadence, meanwhile, offers a growing design IP portfolio, and is a market leader in verification IP. Cadence has focused heavily on memory (DDR) and storage (NAND Flash) solutions, in addition to high-performance interfaces such as PCI Express® Gen 3 and 40/100G Ethernet. In the memory area, Cadence has pioneered IP solutions for DDR4 and Wide I/O. Solutions include controller, PHY, memory models, verification IP, and design-in kits.

In February 2013, Cadence announced an agreement to acquire Cosmic Circuits, a leading provider of analog/mixed-signal IP and PHYs for MIPI®, USB, and power management IP. Upon closing, the acquisition will significantly expand the Cadence® IP portfolio. Here is a quick overview of how Tensilica dataplane IP will complement Cadence and Cosmic CircuitsTM IP:


Why 1+1 = 3 with Cadence and Tensilica

So why the combination of Cadence and Tensilica, and what will the closing of the acquisition mean for SoC engineers? For one thing, the acquisition will further extend the Cadence design IP portfolio beyond interface and analog/mixed-signal IP. But Tensilica will bring Cadence a lot more than just a bigger IP catalog. The acquisition will open new opportunities for configurable IP subsystem integration that would not be possible with two separate companies - and will bring together two top-notch engineering teams that can make that integration happen.

With the acquisition, Tensilica dataplane IP will be backed by Cadence, along with a larger and more scalable support network for IP and tools. The combination will accelerate the delivery and sustainability of the Tensilica IP roadmap. The acquisition will also open the door to tighter integration between Tensilica IP and Cadence EDA tools. This combination will result in faster designs and better power, performance, and area results.

Finally, the acquisition will represent a significant new step by Cadence into the embedded software development market. Tensilica offers an Eclipse-based development environment that can generate a complete software tool chain including a C/C++ compiler, debugger, simulator, and models. SoC designers employing Tensilica Xtensa DPUs can take advantage of the automated Xtensa Processor Generator toolset to customize a DPU core for the exact requirements of each SoC.  When integrated into the Cadence EDA tool flow after closing, this toolset would allow Cadence Silicon Realization tools to further optimize customer SoCs in performance, power and area.

The bottom line: When it closes, the Tensilica acquisition will allow Cadence to deliver configurable, differentiated, application-optimized IP subsystems. These subsystems will provide time-to-market and flexibility advantages over traditional IP integration approaches. This next-generation IP will help pave the way to the advanced SoCs that will empower the world of tomorrow.

To read the press release, click here.

Richard Goering

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.  All others are the property of their respective holders.


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.