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Join EDA “Movers and Shakers” at Electronic Design Process Symposium (EDPS) April 18-19, 2013

Comments(1)Filed under: EDA, Industry Insights, ESL, IEEE, Dan Nenni, EDP, Gary Smith, 3D IC, 3D-IC, Cadence, system-level design, FinFET, EDPS, Monterey, CAD methodologies, design collaboration, Electronic Design Process, TED Talks, EDPS 2013, EDA workshop, Ivo Bolsens

If you're familiar with the popular, cutting-edge TED Talks lecture series, then I would call the Electronic Design Process Symposium (EDPS) the "TED Talks" of EDA. Now in its 20th year, this IEEE-sponsored workshop brings together the thinkers, movers and shakers of IC and systems design to discuss the future of electronic design processes and CAD methodologies.

This year EDPS will be held April 18-19 at the Monterey Beach Hotel in Monterey, California, where crashing surf is directly outside - but that won't distract your attention from the presentations. Prominent topics at the event include system-level design, collaboration in the cloud, 3D-ICs, and FinFET design challenges. This year Cadence is a Gold Sponsor of EDPS, along with Xilinx and NetApp.

EDPS 2012 opening session at the Monterey Beach Hotel

Here are some of the highlights in the EDPS 2013 schedule:

Thursday April 18

  • Keynote by Ivo Bolsens, Xilinx, on "The All Programmable IC at the Heart of Next Generation Embedded Systems."
  • Session 1, ESL and Platforms. Co-chaired by Gary Smith (Gary Smith EDA) and John Swan (Swan on Chips). Presentations from Space Codesign and Cadence. Panel on "How to Make ESL Really Work" with participants from Alcatel-Lucent, Adapt-IP, Docea Power, Space Codesign, and Cadence.
  • Session 2, Design Collaboration. Co-chaired by Naresh Sehgal (Intel) and Camille Kokozaki (NetApp). Presentations from Synopsys, Intel, Nimbic, Xuropa, Intel, and NetApp.
  • Session 3, 3D System Design. Chaired by Herb Reiter (EDA2ASIC). Presentations from Mentor, Cadence, and Micron. Panel on "3D-ICs, Are We There Yet?" with participants from E-System Design, Mentor, Cadence, Micron, Xilinx, Gary Smith EDA, and EDA2ASIC.
  • Dinner and Keynote: Gary Smith, "Silicon Platforms + Virtual Platforms = An Explosion in SoC Design."

Friday April 19

  • Keynote by Dan Nenni, Semiwiki.com, "The FinFET Value Proposition."
  • Session 4, FinFET Design Challenges. Co-chaired and moderated by Aparna Dey, Cadence. Presentations by Oracle, ARM, TSMC, and Synopsys. Panel on "FinFET Foundry Design Enablement Challenges." Participants from GLOBALFOUNDRIES and ARM.
  • Closing comments by John Swan, EDPS 2013 chair.

Further program and registration information is available at the EDPS 2013 web site. Rates go up March 31, so don't delay.

Richard Goering

 

Comments(1)

By John Swan on March 17, 2013
Richard, we have a sum total of 26 speakers and panelists. We are looking forward to an exciting program!

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