Home > Community > Blogs > Industry Insights > dvcon 2013 panel 1 million ic design starts how can we get there
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

Comments(0)Filed under: Industry Insights, DVCon, ASIC, FPGA, SoCs, verification, IC Design, IP Reuse, Functional Verification, Cool Verification, embedded software, J.L. Gray, Costello, high-level models, DVCon 2013, million design starts, Leef, Shenoy, Binyamini, software apps, Zorian, ASIC/ASSP, design starts

If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog, did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per year.

"What do we need to do to make not an incremental improvement, but an order or magnitude improvement?" Gray asked. Indeed, 1 million design starts would be one or two orders of magnitude, depending on whether you're looking only at ASIC/ASSP design starts (6,000-8,000/year, according to Gray) or including FPGA design starts (80,000/year).

Panelists were as follows, listed as shown from left to right in the photograph below:

  • Yervant Zorian, fellow and chief architect, Synopsys
  • Ziv Binyamini, vice president and CTO, System and Software Group, Cadence (see video interview with Binyamini at the end of this blog post)
  • Sunil Shenoy, vice president, new ventures, Intel
  • Serge Leef, vice president, new ventures, Mentor Graphics
  • John Costello, vice president, IC design, Altera

DVCon 2013 "Road to 1M Design Starts" panel (photo by Joe Hupcey III)

Simplifying the Process

To get anywhere near 1M design starts, we will need to make chip design much simpler and less expensive. But as Binyamini (Cadence) noted, chip design is a complicated process that involves many different specialists. "A lot of the time spent building SoCs has to do with the communication breakdown between these people," he said. "I think that one of the biggest ways we could improve the efficiency of chip integration is by setting up something that will allow designers to have an assembly line for SoCs."

Costello (Altera) noted that his company aims to provide silicon so that much of what a designer needs is already built, integrated, and verified. Designers can then develop their own differentiating algorithms and focus verification activities on their added value.

Putting things in perspective, Leef (Mentor) told of visiting a medical device company and finding that they had 32 IC designers, 600 embedded software developers, and 2,000 test engineers. His observation: "It's important to start thinking about an SoC as a building block in a much larger system. People are increasingly adding value with embedded software and system integration."

Zorian (Synopsys) warned that a chip start doesn't end with tapeout. While we have tools and IP for design, we haven't put enough effort into post-silicon validation, he said.

Doing More with Fewer People

Shenoy (Intel) remembered the days when a chip could be designed by one person. "Rather than talking about what resources it would take to get to 1 million design starts, we should probably turn it around and ask what would it take to go back to the days when an SoC could be designed by one person," he said. He also referred to a previous DVCon 2013 panel where panelists had concluded that "it is time to convert back to a more integrated view of design and verification."

Picking up on Shenoy's point about integrated design and verification, Leef called for "semantically aware verification," where you model a processor at a different level of abstraction from the rest of the blocks, and model the memory at a higher level of abstraction. "Ask yourself how the blocks work together, and does the chip work as an application processor. Simulating every gate in memory is not really relevant."

Gray asked audience members whether the models they use are "spot on, bug free, and accurate relative to silicon." Perhaps one hand went up. Binyamini commented that "the question is not really whether models have bugs or not, the problem with some models is that they are not accurate enough by definition. So you need a way to use the proper models at the right time."

A Few Smart People

Should ICs be designed with a small number of very smart people, or a larger number of more "average" people using some kind of established process? This question drew a lot of commentary from panelists.

"Would we get chips out faster by having fewer people work on them? Or do we go for repeatable processes and don't necessarily have superstars?" Shenoy asked. "A big company like Intel is more interested in the latter approach." Costello answered that "a few smart people" is a good for a startup, but as you scale you need processes for people "who are smart but maybe not quite as brilliant."

Another question is whether the embedded software market can provide an example for chip design. Not long ago, Shenoy noted, it was assumed that programmer productivity was around 10 lines of code per day. But now software productivity has "leapfrogged beyond anyone's expectation." Leef noted that his 19-year-old son went from knowing very little about software to publishing his first iTunes app in about six weeks. Total cost: $200.

In software, Leef said, "a lot of development platforms make it possible for people to do a lot of sophisticated things. It's the reuse of software building blocks, and the same thing can apply to hardware." Costello noted, however, that "we're not yet at the point where you can build the hardware equivalent of a software app with one person."

"I don't think hardware is disappearing, but we are moving to use more standard blocks," Binyamini said. "There are more and more ways to capture all the interfaces and connections between different IP. Call it executable specs or metadata, I think it's part of a new paradigm that will allow more efficient creation of chips." As for verification, he said that the "problem of the future is to capture in some formalized way the use cases and drive the process of design and verification from there."

A final question asked about the "business motivation" behind 1 million new chip designs per year. "Ten years ago, we could have asked what's the business motivation for having a million apps," Shenoy retorted. Gray concluded the panel by noting that, as was the case for smartphone apps, "maybe there is something we haven't seen yet. We don't know what it is, but it will come. Are we going to be prepared for it?"

Post-Panel Interview 

In the following short video interview, which immediately followed the panel, I asked Binyamini what it will take to substantially increase ASIC/ASSP design starts; whether the ease of programming software "apps" is a good analogy for future hardware design; and whether the need for many different kinds of specialists stands in the way of a simpler, low-cost IC design flow. If video icon does not open, click here.

 

Richard Goering

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.