Home > Community > Blogs > Industry Insights > archived webinar superspeed usb 3 0 verification challenges and solutions
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Archived Webinar: SuperSpeed USB 3.0, Verification Challenges, and Solutions

Comments(1)Filed under: Industry Insights, SoC, verification, Functional Verification, Verification IP, VIP, UVM, VIP Catalog, USB 3.0, TripleCheck, M-PHY, LTSSM, physical layer, webinarbinar, USB Power Delivery, SuperSpeed USB, USB SSIC, PureSuite, Garg, Super Speed, protocol layer, MIPI PHY, link layer

The growing adoption of SuperSpeed USB (USB 3.0) is enabling some exciting new product designs, but it's also causing a big functional verification challenge. A recently archived Cadence webinar provides an overview of the USB 3.0 protocol, notes IC verification requirements and challenges, and shows how verification IP (VIP) can help.

Huz Dalal, product marketing manager at Cadence, described USB as the "most versatile protocol" and noted that it has continuously evolved since its introduction in the mid-1990s. While SuperSpeed USB supports speeds up to 5 Gbps today, a 10 Gbps SuperSpeed specification is now under development. A USB Power Delivery specification allows more flexible power delivery. And USB SuperSpeed Inter-Chip (SSIC) delivers a scalable chip-to-chip interconnect solution for SuperSpeed USB devices.

Rishubh Garg, USB VIP R&D lead at Cadence, added more perspective. He noted that SuperSpeed USB provides up to a 10X performance increase over USB 2.0, and can use just 1/3 the power of USB 2.0. However, USB 3.0 has a layered architecture that "is very complex compared to USB 2.0 and is very challenging to verify," Garg said.

Thinking in Layers

Garg outlined verification challenges that must be addressed at the protocol, link, and physical layers (right). For example, physical layer verification must consider receiver detection, 8 bit/10 bit encoding/decoding, scrambling and descrambling, serial-to-parallel conversion, clock compensation, and low frequency power signaling (a new USB 3.0 concept). Link layer verification brings in the Link Training and Status State Machine (LTSSM), which defines link connectivity and power management states. Protocol layer verification encompasses bulk streaming and flow control.

USB 3.0 requires a number of verification steps, each with its own unique requirements. These include testing the PHY (physical layer) interface of the upstream or downstream port, link training and the U0 state (the operational state from which packets are transmitted), exercising all possible LTSSM transitions, and various PHY interface tests. Garg gave a detailed description of the verification requirements and tasks for each of these steps.

One way to ease these tasks is to use verification IP, such as that available from the Cadence VIP Catalog, which includes SuperSpeed USB. This VIP "is much more than just a bus-functional model," Garg asserted. He noted that Cadence USB 3.0 VIP includes a PureSuite test library, supports the Universal Verification Methodology (UVM), runs on multiple simulators and platforms, and has been in production for over three years.

What VIP Includes

Garg used the following diagram to show what Cadence USB 3.0 VIP includes. The device under test (DUT) is in the center transmitting data to the bus-functional model (BFM). The VIP monitor makes sure the DUT is transmitting according to the USB protocol. SOMA stands for "specification of model architecture" and it defines timing parameters. The port driver gives control to the DUT to initiate signaling.

Garg reviewed many features of the Cadence VIP solution, including:

  • Dynamic SOMA configuration makes it possible to change timing parameters for LTSSM states
  • Register interface helps control functionality
  • Call-backs make it possible to inject errors and collect coverage
  • Trace capability can reproduce exact test scenario
  • Over 100 protocol violation checks, with controllable severity
  • Support for SSIC with MIPI PHY (M-PHY)
  • Support for On-the-Go (OTG) peripherals
  • Prebuilt PureSuite USB 3.0 compliance test suite

The TripleCheck IP Validator, which I previously blogged about here, will be available for SuperSpeed USB in the near future.

I think this webinar has good information for anyone who is already doing, or is considering, design or verification of a system on chip that uses SuperSpeed USB. You can access the webinar here (Cadence Community log-in required -- quick and free registration if you don't have one).

Richard Goering

 

Comments(1)

By James Colgan on March 1, 2013
Any engineer can try out the USB SuperSpeed Inter-Chip (SSIC) VIP hands-on on the cloud ht.ly/ibcQD.  FREE of charge, with no download or installation.

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.