As I wrote in a January 2013 blog post, a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation, the need to improve performance is acute. A newly-published Cadence whitepaper, "Gate-Level Simulation Methodology," sets forth best practices for improving the performance of gate-level simulation.
The whitepaper notes that gate-level simulation is increasing due to complex timing checks at 40nm and below, design for test (DFT) insertion at the gate level, and low-power considerations. Gate-level simulation overcomes the limitations of static timing analysis (STA), such as the inability to identify asynchronous interfaces. It's used to verify reset sequences and to detect situations in which the RTL simulator "optimistically" assigns a 1 or 0 to a signal that should be X (unknown).
Gate-level simulation can begin as soon as a gate-level netlist is synthesized. A typical RTL to gate-level netlist flow is shown below.
Although design teams are finding they need to run more gate-level simulation as process nodes shrink, many are still using methodologies developed in the 1980s when gate-level simulation began. Since the size of today's designs was almost inconceivable in the 1980s, a new gate-level simulation methodology is needed, the whitepaper notes.
The detailed whitepaper has two parts. The first part shows how various features in the Cadence Incisive Enterprise Simulator can maximize cycle speed and minimize memory consumption. The second part details general steps you can take with any simulator, synthesis tool, DFT engine, and logic equivalence checking engine. All gate-level simulation users will find value in this section.
Improving Gate-Level Simulation with Incisive
The first part of the whitepaper shows how the Incisive Enterprise Simulator provides features that let you do the following:
- Apply zero-delay simulation, which runs much faster than simulation with full timing
- Use built-in delay mode control functions to reduce simulation time
- Selectively disable delays in sections of the model where timing is not currently a concern
- Detect potential zero-delay gate loops
- Correct race conditions that occur in zero-delay mode
- Disable timing checks for the entire simulation, or for selected blocks
- Control the number of timing check violations
- Use wave dumping only if required
- Avoid, or use selectively, command-line options that provide additional information and access to objects for debugging
- Use "multi-snapshot incremental elaboration" to improve elaboration performance
Methodologies for Improving Gate-Level Simulation
The second part of the whitepaper offers a more general look at methodologies that can help reduce overall gate-level verification time. First, it shows how to effectively use static tools, like linting and static timing analysis, to reduce gate-level simulation time. Linting, for example, should be used before running zero-delay information. Static timing analysis can provide information that's used to start gate-level simulation with timing early in the flow. This figure depicts a static timing analysis and gate-level simulation flow:
Other points covered in the whitepaper include:
- Generating and using "smart SDF" (Standard Delay Format files) with timing abstractions
- Controlling or handling timing checks based on STA reports
- Using Design for Test (DFT) verification
- Black-boxing modules based on test activity
- Saving and restarting simulations
In short, gate-level simulation performance is not just about faster engines or simulation features - it's also about the methodology you apply. This whitepaper explores new use models and methodologies that can boost gate-level simulation productivity. Using these approaches, you can focus on verifying real gate-level issues rather than spending time re-verifying working circuits. You can access the whitepaper here.
Related Blog Posts
Functional Verification Survey - Why Gate-Level Simulation is Increasing
Webinar Report: Speeding RTL and Gate-Level Simulation