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DVCon 2013 Lunch Panel: Best Practices in Verification Planning

Comments(1)Filed under: Industry Insights, DVCon, verilab, Functional Verification, Xilinx, UVM, Stellfox, Cadence, vPlan, Oski, Brennan, Maxim, DVCon 2013, verification planning, expert panel, Paradigm Works, DVCon lunch panel

While standardized methodologies guide many other aspects of functional verification, planning the verification process is as much an art as a science. How can you know if you're following "best practices" in verification planning? One way to find out is to attend a Cadence sponsored luncheon panel at the DVCon 2013 Conference in San Jose, California Wednesday Feb. 27 from 12:00 p.m. to 1:15 p.m.

The Best Practices in Verification panel will be moderated by John Brennan, Product Director for verification at Cadence, and will feature the following expert panelists:

  • Jason Sprott - Chief Technology Officer, Verilab
  • Mike Stellfox - Verification Fellow, Cadence Design Systems
  • Dr. Ambar Sarkar - Chief Verification Technologist, Paradigm Works
  • Neyaz Khan - Distinguished Member of Technical Staff, Maxim Integrated
  • Vigyan Singhal - President and CEO of OSKI Technology
  • Meirav Nitzan - Lead Verification Methodologist, Xilinx

The panel will provide an open discussion about what's working and what's not, and will consider such topics as creating a verification plan, preventing bug escapes, planning automation, avoiding over-planning, tracking and merging coverage from multiple technologies, and human factors to consider.

I asked Brennan why there's a need for a panel on verification planning. He noted that while other areas of verification are "pretty well codified" by methodologies such as the Universal Verification Methodology (UVM), "planning is still somewhat of an art form, and there's more wiggle room in how you should do it. So people are always asking what the best approach is."

UVM is about "how" to do verification, and verification planning is about "what" to verify, Stellfox added. "How do you quantify, in a very thorough way, the features of the design that need to be verified? How do you capture the metrics that allow you to measure your progress towards achieving that plan? These questions have gained a lot of interest."

Stellfox hopes attendees will come away with more understanding of the importance of planning, the diversity of verification techniques, the scope of verification planning, the methods and tools in use today, and techniques for leveraging pre-verified IP blocks. As a panelist, he'll also take a broader view of "the next set of challenges" including hardware/software SoC verification and analog/mixed-signal verification.

While the lunch panel is open to conference attendees, seating is limited, so if you want to hear this expert panel, come and get a seat early! You can also attend a paper session on "Best Practices in Verification Planning" Tuesday during Session 4, 1:00 p.m. - 3:00 p.m. You can find further information about the panel here and view the entire DVCon schedule, and register, here.

Richard Goering

 

Comments(1)

By Dr. asheesh Shah on February 25, 2013
the topic of my phd thesis is same and proposes a framework  with verification planning as the central theme...if anyone interested let me know..

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