10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer at Cadence, and was part of a session titled "Next Generation R&D and Advanced Tools for 14nm and Beyond."
Gerousis discussed "second-generation" double patterning at 10nm, double-patterning aware placement and routing, and FinFET custom design challenges. He showed a FinFET-ready custom design flow and digital flow, and discussed two 14nm FinFET test chip tapeouts that involved Cadence and ARM - one with an IBM silicon-on-insulator (SOI) process, and one with a Samsung bulk CMOS process.
Collaboration was the overall theme of the one-day conference, and Gerousis noted the close work that Cadence is doing with ARM and the Common Platform partners. "The earlier we engage as the nodes go down, the better we can optimize the cell architecture as well as optimize the toolset," he said. "Right now we're dealing with 10nm and we are affecting the cell architecture as well as the routing technology, and we are also optimizing the rule set that's supported at this node."
Double Patterning Changes at 10nm
If you've read anything about the 20nm node, you're probably aware of double patterning, which uses two masks to create patterns that today's lithography equipment can correctly print. At 20nm and 14nm designers will most likely use a technique called litho-etch, litho-etch (LELE), and it's about like it sounds - expose and etch repeatedly using alternating masks.
At 10nm, however, tighter pitches will call for a different technique called sidewall image transfer (SIT) or self-aligned double patterning (SADP). This is a much more complex process that includes creating relief patterns, depositing sidewall spacers, and trimming away everything that's not needed to produce the required shape. As shown below, exposure with a "block mask" removes unwanted features. Gerousis noted that the design must be not only "two color mappable" but also compliant with block mask design rules.
There's more to "second generation" double patterning. A third color on the M1 layer can eliminate layout conflicts, and help maintain established design styles and cell architectures. The Mx layers above M1 must be two-color mappable and block mask rule compliant. Some trimming of blockages is needed to get target patterns to print correctly, and trim shapes need to follow block mask rules such as width and spacing.
Regardless of the method, double patterning requires color-aware placement. At 10nm, however, there are some new constraints on boundary conditions that tools must understand in order to avoid double patterning conflicts. Correct-by-construction, double-patterning aware placement is also a requirement, and is supported by the Cadence Nanoroute router for 20nm and 14nm.
At 10nm, SIT double patterning will introduce a new class of design constraints for the router. "What a router needs to do," Gerousis said, "is to address the color-mappable rule set and all associated topology with the block mask. That's very difficult from a technology aspect." He noted that Cadence, ARM, and Common Platform partners are collaborating on this new routing technology and are working towards a prototype demonstration with a test chip.
Custom and Digital FinFET Design Flows
Gerousis noted that 14nm and 20nm share many of the same challenges - double patterning, layout dependent effects, local interconnect, complex design rules, and device and interconnect variation. The main thing that's new at 14nm is the FinFET architecture. One much discussed challenge is "quantized transistor width." Custom designers can no longer use arbitrary transistor widths - they can only change the number of fins.
Here are some other points custom designers need to keep in mind about FinFETs:
- Cell height is determined by both the number of metal tracks and the number of fins. This affects cell design and floorplanning.
- Transistor width is determined by the integer number of fins. A tight fin pitch enables the best efficiency.
- A "sea of fins" extends over many poly tracks. Fins need to be on a grid, and individual transistors have to be snapped to the fin grid.
- Transistor-level extraction must examine the 3D FinFET structure for both resistance and capacitance - and do so quickly. (The Cadence QRC extraction engine provides this capability).
The Cadence FinFET flow for circuit design and simulation is shown below. Cadence also helped develop the BSIM-CMG FinFET device model, as described in a recent blog post.
Cadence has also developed a 14nm FinFET digital implementation flow (below) based on the Encounter Digital Implementation System. This flow allowed Cadence, ARM and Samsung to complete a 14nm FinFET test chip project in just 8 weeks, as noted in a previous blog post. The flow, said Gerousis, uses "color awareness everywhere. You can input cells with no color and we can colorize them. We do placement and floorplanning and routing with colors. Now we're extending that to 10nm."
Proof in Silicon
Gerousis talked further about the collaboration with Samsung, noting that it actually involved two test chips - one consisting of SRAM macros, and another based on the ARM Cortex-A7. Here, he said, the Encounter Digital Implementation System was used for double-patterning aware placement, routing, timing, and design rule checking. He also discussed another 2012 test chip tapeout involving Cadence, ARM, and IBM's 14nm SOI process that used the Cortex-M0 processor (described here).
It will be some time yet before 14nm FinFET technology, let alone 10nm, goes into full volume production. But extensive work is clearly underway to make these technologies as automated and as optimized as possible.
Related Blog Posts
Common Platform Forum Keynotes: 14nm FinFETs and beyond
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
ARM TechCon: Design at 14nm (or 10nm) - What's Going to Change
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs
FinFETs, Tri-Gate Transistors Promise Low Power - But Pose Some Design Challenges
Cadence, ARM, Samsung 14nm Test Chip - Collaboration Eases FinFET Digital Implementation
BSIM-CMG FinFET Model - How Academia and Industry Empowered the Next Transistor