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Common Platform Forum Keynotes: 14nm FinFETs and Beyond

Comments(0)Filed under: Industry Insights, ARM, lithography, FinFets, Global Foundries, IBM, HKMG, EUV, Double Patterning, 3D, GlobalFoundries, collaboration, Patel, 20nm, Patton, 3D-IC, Cadence, common platform forum, common platform, Samsung, Internet of Things, mobile devices, Cortex-M0, Cortex-A9, FinFET, Cortex-A7, Kim, 14nm, photonics, 10nm, sidewall image transfer, triple patterning, nano-photonics, 7 nm, FinFET challenges, self-assembly, 14XM, carbon nanotubes, Noonen, process variations, 3D extraction

How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing, revealed some of the latest developments underway at IBM, GLOBALFOUNDRIES, Samsung, and ARM.

The most expansive speech - in terms of diverse technologies, and time - was by Gary Patton (right), vice president of the Semiconductor Research and Development Center at IBM. He covered topics including FinFETs, extreme ultraviolet (EUV) lithography, carbon nanotubes, directed self-assembly, photonics, and more. These technologies will lead to new generations of powerful mobile devices, wearable electronics, implanted devices, and other products that will result from the "pervasive use of electronics, everywhere and in everything," Patton said.

"There is a lot of turmoil about where we're going because we're at a discontinuity," Patton said. What's happening is that we are running out of ways to scale planar transistor technology. As a result, "we are moving into the 3D era, and we're talking about 3D devices [FinFETs] and 3D chip stacking." And beyond that is the "atomic dimension era" that will bring in new materials like carbon nanotubes. As Patton showed, "atomic dimension" research is now well underway.

One big bump in the road is lithography - and here comes a disappointment. EUV, the technology that everyone has been counting on to enable advanced node silicon, is still not ready and probably won't be until the 7nm node, Patton said. So, IBM and its partners are developing technologies that will permit yet another extension of today's immersion lithography. These technologies include double and triple patterning, sidewall image transfer, and directed self-assembly.

FinFET Advantages and Challenges

Patton said that IBM is "driving FinFETs very, very hard" and working with EDA partners to develop solutions that will allow designers to get full benefits from these 3D devices. A FinFET, he noted, is a fully depleted device. You wrap a gate around a transistor and fully deplete it, resulting in better electrostatic characteristics, stronger gate control, and better SRAM performance.

The problem, Patton said, is that "existing FinFETs struggle from a performance and variability perspective." One problem is the fin profile shape. You'd like to have a nice slanted profile that makes it easy to fill the dielectric between the fins, but this creates a design that drags down performance and introduces variability. So, IBM has done a lot of optimization work to produce vertical profiles. Too few fins can also cause variability, so IBM has optimized its process to provide uniform characteristics down to one fin. A third problem, also addressed by IBM, is non-uniform fin doping.

The next device innovation, Patton predicted, will be carbon nanotubes, which will essentially replace the fins on a device that still looks much like a FinFET. But what a difference - "because of the great transport properties of carbon, you can get a 10X improvement in power or performance," Patton said. Two challenges remain. One is that about 30% of the carbon nanotubes that are created are metallic, and must be sorted out. Another is placing the nanotubes where you want them on the wafer.

Beyond Double Patterning

While double patterning (the use of two masks to print alternating features) will make immersion lithography practical at 20nm, a new approach will be needed at 10nm, Patton said. This will be sidewall image transfer (also called self-aligned double patterning) and it's quite a bit more complex than today's "litho-etch, litho-etch" methodology. Sidewall image transfer involves a number of steps including depositing a film, etching it to create a sidewall, and then using a "cut mask" to get the structure you want.

What happens at 7nm, where triple or even quadruple patterning may be needed? An alternative and less costly solution, Patton said, is to use block co-polymers. If you create an anchor pattern and apply the proper constraints, the co-polymers will align themselves in alternating parallel patterns. You then cut away what you don't want. This practice is called directed self-assembly (DSA).

Patton concluded his talk with a look at photonics, which could provide a huge boost in the ability to move data quickly and reliably. He showed a "cost efficient" example of a modulator that uses photonics alongside CMOS logic circuitry, achieving a performance of 25 Gbits/second. His "ultimate" vision integrates photonics with 3D ICs. Patton says such a design could include a photonics plane, a memory plane, and a logic plane. He envisions 300 cores, 30 Gbytes of eDRAM, and bandwidth of 1 Terabyte/second. One can only imagine how such a technology could be used.

Putting FinFETs Into Silicon

Mike Noonen (left), executive vice president for global sales at GLOBALFOUNDRIES, presented a foundry perspective on 14nm FinFETs. He noted that his company announced its 14XM FinFET process in 2012, that it's currently undergoing testing, and that multi-project wafer shuttles will be available by the end of this year. 14XM will ramp to production in the first half of 2014. "We're also looking ahead to our 10nm FinFET family, which will be entering the test qualification stage at the end of 2014 and moving into production in the second half of 2015," he said.

Noonen noted that GLOBALFOUNDRIES leveraged its successful experience with high-k metal gate (HKMG) technology to develop this 14nm process. He said the foundry has minimized the number of double-patterning layers needed for back end of line (BEOL), and has developed "fin friendly" design rules that will allow an easy port of silicon IP.

He also had some interesting data from collaborative work between GLOBALFOUNDRIES and ARM.  The companies compared an ARM Cortex-A9 dual core design in a 28nm SLP process (12-track library) to the new 14MX process (9 track library). If you keep the performance constant, they found, you can achieve a 62% power savings from 28nm to 14nm. Or, you can keep power constant, and see a 61% performance increase. "This really is proof positive that moving to FinFETs can have a dramatic impact on power and performance," Noonen said.

FinFETs - Still Some Work to be Done

Another foundry perspective came from K.H. Kim (right), executive vice president of the foundry business at Samsung. He offered more of a "deep dive" into the design challenges of FinFETs and possible solutions. While we've used planar transistors for decades, he said, "there's not much juice left - so we have to move on to FinFET technology, otherwise we cannot survive."

FinFETs benefit from a fully depleted channel, Kim noted. They can provide a significant delay improvement at a lower Vdd, or a much lower Vdd at the same delay. But FinFETs pose the following challenges:

  • Process variations and parasitics. FinFET characteristics depend on fin width and height uniformity. Parasitic resistance crosses over strained silicon channel resistance due to the narrow source/drain width.
  • Channel width and drive current choices. While planar transistors support an unconstrained selection of device widths, all fin widths and heights are identical. Thus, to change drive strength, only a "quantized" channel width is available in a FinFET (i.e., adding fins in discrete increments).
  • 3D modeling and extraction. 3D device modeling is needed to capture fin profile data and geometry shapes. Complex middle-of-line parasitic modeling is needed.

But deep collaboration through the Common Platform is addressing these challenges, Kim said. For example, this collaboration has resulted in an advanced tool for fins and spacers, and an advanced middle-of-line scheme that provides a Shottky barrier height modulation. Kim also mentioned the work Samsung has done with EDA partners on device modeling and extraction, including work with Cadence on Spectre (for device modeling) and QRC (for parasitic extraction).

Kim noted that Samsung participated in some 14nm announcements in 2012, including a collaborative effort with ARM and Cadence that implemented a Cortex-A7 based test chip using FinFET technology (see my earlier blog post about that development here).

Kim said that Samsung's 14nm FinFET process is "on track" and that multi-project wafers will be available this year for early adopters. A new Korean fab will go on-line in late 2014 or early 2015 and provide an "assurance of supply," he said.

A World of Connected Devices

The final keynote speaker was Dipesh Patel (left), executive vice president and general manager of the physical IP division at ARM. He mostly talked about how the world is changing due to mobility - in a world with 5 billion mobile devices! But he also mentioned some of ARM's work on 14nm FinFET processes. This includes a 2012 project with IBM and Cadence to tape out a Cortex-M0 based test chip (blog post here). He also noted the Cadence-ARM-Samsung 14nm test chip that Kim talked about.

"There is a lot of opportunity in any space you can look at," Patel concluded. "Mobile devices, smart phones, tablets, servers, the Internet of Things - there are diverse sets of devices and applications. All this is possible because of the collaboration we are doing. It is collaboration leading to real products. It is collaboration designed to reduce your time to market and the risk you would face going into production."

You can view the keynotes here.

Richard Goering

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FinFETs, Tri-Gate Transistors Promise Low Power - But Pose Some Design Challenges

Cadence, ARM, Samsung 14nm Test Chip - Collaboration Eases FinFET Digital Implementation

 

 

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